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DARPA 3DSoC developed high performance 3D ICs based on CNT FET for future DOD computation systems

Deployed electronic systems increasingly require advanced processing capabilities, however the time and power required to access system memory – commonly referred to as the “memory bottleneck” – takes a significant toll on their performance. Any substantial improvement in electronic system performance will require a radical reduction in memory access time and overall dynamic power of the system. The use of a monolithic three-dimensional system-on-chip (SoC) stack to integrate memory and logic is one approach that could dramatically alter the memory bottleneck challenge. However, developing an effective 3D SoC stack would require increasing the width of buses to memory through much finer pitch interconnects, while simultaneously decreasing the resistor-capacitor (RC) delays through much shorter interconnect lines in the SoC


To address the memory bottleneck problem, the Three Dimensional Monolithic System-on-a-Chip (3DSoC) program seeks to develop the monolithic 3D technology required to build logic, memory, and input/output (I/O) on a single die using a legacy lithography node while improving performance by more than 50X when compared with leading edge technology nodes. To achieve its goals, 3DSoC seeks to develop fabrication technology as well as the design flows required to take advantage of the technology’s capabilities.


The 3DSoC program aims to drive the future of computation architecture, removing the limitations of the current 2D approach to SoC design and manufacturing. The resulting fabrication technology is intended to be based at a U.S. manufacturing facility, which will allow Department of Defense (DoD) entities to have easy access to the technology, tools, and manufacturing capabilities to explore and build future computation systems that will deliver 50X better performance at power results and improve the performance of future DoD systems.


CNT FET Transistors

Carbon nanotube transistors are finally making progress for potential use in advanced logic chips after nearly a quarter century in R&D.  Several government agencies, companies, foundries, and universities over the years have been developing, and are now making advancements with carbon nanotube field-effect transistors (FETs), as well as newer versions integrated with memory. Carbon nanotubes are basically tiny rolled-up cylindrical sheets of graphene. But even though they exhibit better electrical and thermal properties than silicon, synthesizing high-purity tubes and integrating them into chips has been a major challenge. That’s why carbon nanotube FETs have been pushed out over the years, and are still not in mass production today.


In theory, though, carbon nanotube FETs can outperform today’s finFETs and perhaps other next-generation transistor types in R&D. Targeted for beyond the 3nm node or before, carbon nanotube FETs also are appealing because they resemble and operate like today’s conventional planar transistors, and may even extend planar to advanced nodes with immunity to short-channel effects. These devices are different than carbon nanotube RAMs, which are also in the works.


Like traditional transistors, which act like switches in devices, a carbon nanotube FET consists of a source, drain, and gate. The big difference is the channel, which allows electrons to flow from the source to the drain. In today’s transistors, the channel is based on silicon. In contrast, a carbon nanotube FET makes use of a fixed number of tiny and parallel nanotubes for the channels, each measuring 1nm in diameter. Leveraging the properties of these materials, carbon nanotube transistors exhibit high mobilities at low power.


In addition, carbon nanotube transistors are fabricated at lower temperatures. “That makes it possible to build things in 3D. Many memory type devices also can be made at low temperatures. So there is an opportunity to build chips in 3D with highly dense connections between the memory and the logic device,” said H.-S. Philip Wong, a professor in the School of Engineering at Stanford.


The DARPA 3DSoC program, which began in 2018, has realized several technical achievements after running a wide variety of test chips to improve CNT manufacturability and reliability.


DARPA 3DSoC CNFET project moves towards commercialization phase

The first phase focused on transferring the Carbon Nanotube Field Effect Transistor (CNFET)-based 3DSoC technology into SkyWater’s 200mm production facility . Phase two will focus on refining manufacturing quality, yield, performance, and density.


Skywater, the US government trusted fab partner, and MIT   announced in August 2020 that the DARPA Three Dimensional Monolithic System-on-a-Chip (3DSoC) programme, has entered its second phase. After completing the program’s initial phase, focused on transferring the Carbon Nanotube Field Effect Transistor (CNFET)-based 3DSoC technology into SkyWater’s 200 mm production facility, phase two will focus on refining manufacturing quality, yield, performance, and density – key elements of commercial viability.


The 3DSoC program aims to shift cost/performance benchmarks that have been the standard for decades. This new paradigm is expected to accelerate AI and advanced computing across use cases in autonomous vehicles, medical/healthcare diagnostics, edge computing, wearables, and IoT applications.


A 3DSoC program update was  presented by MITprofessor, Dr. Max Shulaker at the virtual 2020 DARPA Electronics Resurgence Initiative (ERI) Summit on August 20th. The programme team’s work on the 3DSoC program was presented in June at the virtual 2020 Symposia on VLSI Technology and Circuits, highlighting BEOL monolithic 3D integration of CNFETs + RRAM and first hardware demonstrations of the monolithically integrated 3DSoC technology with SRAM and RISC-V compute core.


The update also covered the team’s development of an industrial-grade foundry process design kit (PDK) for the 3DSoC technology platform, which marks a significant milestone to enable customer designs in SkyWater’s Early Access Program.


Additionally, the work on foundry integration by MIT and SkyWater was published recently in Nature Electronics demonstrating the methodologies employed to volume manufacture CNTs on 200 mm wafers in the same commercial facilities that fabricate silicon-based transistors. This important step in taking CNTs from the lab to the factory floor paves the way for more energy efficient, 3D microprocessors.


Notably, the technology enables the ability to monolithically integrate stackable tiers of CNT-based logic and RRAM to realize a high-density, high-bandwidth SoC architecture, all with low temperature fabrication techniques.


While this is anticipated to accelerate AI and advanced computing, it also opens new dimensions of innovation and potentially enables backend logic integration with non-silicon substrates. This development would bring new possibilities for monolithic heterogeneous integration, which will lead to on-chip logic for new imaging, smart sensors, power management, and many other undiscovered applications.


“We are excited to continue this journey with MIT to fulfill the unique promise of carbon nanotube technology to the semiconductor industry, with disruptive implications for artificial intelligence and leading-edge computing applications across commercial and defense industries,” said Dr. Brad Ferguson, SkyWater Chief Technology Officer.


Added Thomas Sonderman, SkyWater President, “This program is proving the viability and scalability of CNFETs and demonstrates SkyWater’s broader commitment to support the resurgence of advanced manufacturing capabilities in the U.S.” “It is really exciting to take this giant step forward and hit milestones inside of a foundry environment, making this leap into production. This marks a time for the industry to take notice of CNTs as a much more energy efficient alternative than silicon-based transistors and prepare product roadmaps for this disruptive technology,” said Dr. MaxShulaker, MIT Professor of Electrical Engineering and Computer Science.



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