Electronic ADCs are embedded ubiquitously in numerous everyday items, such as mobile phones, digital cameras and computer mice. As the speed of electronic ADCs continues to increase, more and more sophisticated applications including medical imaging, 60GHz wireless communications and cognitive radar can benefit from the use of ADCs and digital signal processing, which are all important to our society and economy.
U.S. Defense Department researchers recently announced the development of an analog-to-digital converter chip that processes signals at the previously unheard of rate of 60 billion times per second—fast enough to process vast majority of radar, communications and electronic warfare signals in contested and congested electromagnetic environments.
“Our society is highly connected through various digital services. However, much of the information we exchange and process is of an analogue nature in its origin. Analogue-to-digital conversion is thus already an integral part of our modern digital society. Digital signal processing is a powerful technique for storing, analysing and manipulating digital signals. Ultimately, the quality of the signal to be processed is determined by the performance of the analogue-to-digital converter (ADC) which is used to sample the original analogue signal in the first place and produce a digital representation of it,” writes Dr Chin.
Competition for scarce electromagnetic (EM) spectrum is increasing, driven by a growing military and civilian demand for connected devices. As the spectrum becomes more congested, the Department of Defense (DoD) will need better tools for managing the EM environment and for avoiding interference from competing signal.
The performance of digital receivers used in modern radar, communication, and surveillance systems is often limited by the performance of the analog-to-digital converter (ADC) used to digitize the received signal. Ultrafast ADCs are critical in military applications such as military software-defined radio, radar, and electronic counter-warfare (ECW) that require high sampling rates and large bandwidths.
Software Defined Radios
Modern military tactical and battlefield radio systems involve a wide range of frequencies, numerous waveforms, rapid software reconfiguration requirements, and highly dynamic RF environments. Software-defined radio (SDR) uses software to replace the hardware components of a radio communication system to offer greater flexibility and security, particularly for military communications.
The ideal SDR architecture connects a high-performance analog-to digital converter (ADC) to the antenna and moves many of the typical RF functions such as filtering, demodulation, and other processing to the digital realm. A Gsps-capable ADC makes it possible to combine multiple
narrowband and wideband channels into one ultra-wideband channel. This moves formerly analog channelization onto the FPGA, where frequencies and bandwidths can be dynamically controlled
with software to maximize system flexibility and reconfigurability.
For this reason, SDR has become the go-to solution for military radio designs by enabling universal full-duplex radio systems that can be used across many platforms and reconfigured as needed in the field. SDR is a key component of the communications systems of unmanned aerial vehicle (UAV) and, increasingly, unmanned ground vehicle (UGV) platforms. The SDR can also simultaneously monitor many frequencies, which is invaluable for radar systems or electronic warfare where it enables the detection of echoes or jamming threats.
Electronic warfare Receivers
EW systems, which identify and counter electronic threats such as surveillance and tracking radar systems, are commonly categorized either as electronic support (ES), electronic attack (EA), or electronic protect (EP) systems. ES systems intercept and measure signal parameters to identify source and perform threat analysis.
Threat detection from unknown targets in these systems requires a receiver which can operate over a wide frequency band to identify threat signals and initiate countermeasures. Typical EW systems may operate from DC to 20 GHz. One of the key building blocks critical for any EW system is the analog-to-digital converter (ADC), which results in a relentless push for high performance and low cost, as limits for high-speed ADCs in these EW systems.
Today’s ADCs, however, only process data within a limited portion of the spectrum at a given time. As a result, they can temporarily overlook critical information about radar, jamming, communications, and other potentially problematic EM signals.
DARPA’s Arrays at Commercial Timescales (ACT) program
DARPA’s Arrays at Commercial Timescales (ACT) program addressed this challenge by supporting the development of an ADC with a processing speed nearly ten times that of commercially available, state-of-the-art alternatives. By leveraging this increased speed, the resulting ADC can analyze data from across a much wider spectrum range, allowing DoD systems to better operate in congested spectrum bands and to more rapidly react to spectrum-based threats.
The new ADC samples and digitizes spectrum signals at a rate of over 60 billion times per second (60 GigaSamples/sec). That’s fast enough to directly detect and analyze any signal at 30 GHz or below—a range that encompasses the vast majority of operating frequencies of interest. Whereas scanning through these frequencies today requires costly application-specific hardware with long development cycles, the new ADC can provide a “one-stop shop” for processing radar, communications and electronic warfare signals.
The advance was enabled by 32 nm silicon-on-insulator (SOI) semiconductor technologies available through DARPA’s ongoing partnership with GlobalFoundries, a manufacturer of highly-advanced semiconductor chips.
However this chip also generates staggering amount of data, reaching nearly a terabyte per second. This high data rate requires on-chip data-management circuitry that allows signals to be processed locally on the ADC, reducing the amount of data that must be communicated to neighboring electronics. This on-board digital signal processing burns quite a bit of power and also demands state-of-the-art transistors.
The chip also draws far too much power, by using GlobalFoundries’ even more advanced 14 nm technology, ACT’s next generation of ADCs aim to reduce power requirements by an additional 50 percent and enable yet smaller and lighter systems that can sample even greater swaths of the spectrum.
DARPA’s next step is to figure out where and how the ADC first may be used. Olsson suggests that the converter may offer situational awareness of the radio frequency (RF) spectrum. “We’re very early on in the exploration of the analog-to-digital converter chip. We just recently achieved this level of performance, and we’re looking [to determine] how we can leverage it to give us information or cognition about what’s going on in our radio frequency environment,” he explains.
For example, the ADC could “take in this broad swath of RF spectrum and see where there are RF emitters in your spectrum,” Olsson offers. He hypothesizes that it could be integrated into a Humvee, “where maybe power consumption isn’t the biggest problem you have,” and then later adapted to “the handheld soldier level, where energy efficiency becomes much more critical.”
Spectrum situational awareness is more vital and more challenging in the military sector than in other domains. “The interference in a commercial application really isn’t very strong. In a Defense Department application, we have dynamically changing RF environments that are not preplanned. We don’t know what to expect, and so our transmitters and receivers need much higher performance,” Olsson states
“The ACT program is really about building common hardware that can be reused across many different RF systems. That will allow us to share the development cost and reduce the time frame … so that the department can upgrade its hardware [just as] Apple upgrades the hardware in its iPhone every couple of years, rather than it being a 10-year development and upgrade cycle,” says Troy Olsson, DARPA’s Arrays at Commercial Timescales (ACT) program manager. Program officials estimate that developing a new phased array—and upgrading it when necessary—will take about half the time it does today.
While radio frequency (RF) electronic data converters are now running at unprecedented sampling rates, Aperture jitter i.e. inability of ADCs to sample at precisely defined times has been a major bottleneck on the way towards higher speeds and better accuracy. Photonic ADCs, operating with very low timing jitter, are envisaged to bring ADC performance to new levels.
Photonic ADCs, which perform sampling using ultra-stable optical pulse trains generated by Ultra-stable mode-locked lasers with jitter levels many orders of magnitude lower exist today could improve ADC performance by orders of magnitude.
“This jitter scaling from microwave to optical sources, together with rapid progress in electronic-photonic integration via the silicon photonics technology platform, gives confidence that the 3-4 orders of magnitude in jitter reduction, possible with mode-locked lasers, can be exploited to bring ADC performance to levels well beyond what is possible today,” write Anatol Khilo, Steven J. Spector and others.
£470k funding for Novel photonic sampling
Dr Chin-Pang Liu whose research project titled ‘Photonic Sampling using an Agile Optical Comb Generator’ has received over £470,000 funding.
Photonics has been used to increase the performance of electronic ADCs since the 1970s, forming what is now generally termed the photonic ADC. Most photonic ADCs with sampling rates as high as 1 THz (or 1,000,000,000,000 Hz) have employed mode-locked lasers, as they can produce very high power optical pulses with very short pulse widths and low jitters, both in the fs region. Such optical pulses are ideal for sampling microwave and millimetre-wave signals in conjunction with a Mach Zehnder modulator (MZM) or a photo-conductive switch as reported in previous work from the Photonics Group at UCL.
The overall project objective is to investigate experimentally a novel, low-jitter sampling technique using a frequency agile optical comb generator for microwave and millimetre-wave signals. Compared to the traditional approach using bulky and expensive mode-locked lasers with inflexible sampling frequencies, Dr Liu’s proposed technique based on an optical comb generator allows highly adjustable sampling frequencies to suit the different centre frequencies and bandwidths of the input signals.
These attributes are important for the next 10 to 50 years as the lower parts of the radio spectrum become congested by increasing numbers of higher throughput wireless services, and society and policy makers in the UK and elsewhere are forced to use frequency bands at 60 GHz or higher. Dr Liu expects his technique to find applications and generate impacts in a wide range of areas, including radar systems, medical imaging and wireless-over-fibre communications.
DARPA’s Remoted Analog-to-Digital Converter with De-serialization and Reconstruction (RADER)
Real-time assessment of the electromagnetic environment can provide a key tactical advantage. The rapid development and proliferation of advanced radios, however, has made this a challenging task. Radio frequency (RF) sensor systems on the modern battlefield must cover many RF and microwave bands through noise and powerful interferers.
Ultra-wideband analog-to-digital conversion (ADC) has emerged as an essential technology to interface between propagating analog RF signals and digital processing for reactive decision-making. Such an ADC allows for high-speed and reconfigurable digital processing in a complex electromagnetic environment.
Despite the significant military need, progress in high-resolution, high-speed ADC systems has slowed. This can be attributed to fundamental limits of the timing jitter of the ADC clock and sample-and-hold circuits in conventional ADCs. Optical mode locked lasers have demonstrated timing jitter that is orders of magnitude better than electronic approaches. An architecture employing optical sampling could overcome jitter limitations of all-electronic ADCs.
DARPA’s RADER program seeks to dramatically enhance direct ADC conversion of remote signal inputs, over a broad instantaneous bandwidth, for enhanced signal collection with high dynamic range for target detection in cluttered electromagnetic environments.
The RADER program seeks to achieve ADC conversion over a 10 GHz bandwidth with 10 effective bits of resolution and 63 dB of spur free dynamic range through the incorporation of a photonic front-end. RADER aims to develop low-jitter sampling sources, novel photonic ADC architectures, and backend signal processing algorithms necessary for such a high performance ADC system. The final system may be capable of remoting signals over 50 meters and operating under 50 Watts.
DARPA’s Direct Sampling Digital Receiver (DISARMER)
Conventional analog-to-digital converters (ADCs) are fundamentally limited by timing jitter in the sampling source, forcing a trade-off between bandwidth and resolution. As a result, radio frequency (RF) systems are typically designed with narrow-bandwidth channels. These engineering constraints present problems when faced with broadband signals and ultra-short pulses. At high carrier frequencies, RF systems are further limited by the tuner that must mix down to baseband for electronic digitization.
The DISARMER program seeks to build an ADC with a photonic sampling source that directly digitizes the X-band (8-12 Gigahertz) instantaneously and coherently with greater resolution than a conventional electronic system. Through reduced timing jitter and elimination of the RF tuner, DISARMER aims to demonstrate signal fidelity more than 100 times better than the state of the art. DISARMER will produce an integrated electronic-photonic chip, mode-locked laser, and backend processor that outputs streaming digital data
US DOD’s SBIR: Increased Radio Frequency (RF) Sampling & Radar Architecture Upgrades
OBJECTIVE: Validate the use of analog to digital converters (ADC), with higher sample rates and wider word lengths, to improve radar detection. Explore architecture upgrades which will allow rapid insertion of faster ADC, processor, and bandwidth technology
In the first look, first kill environment, detection range becomes critical when going up against threats with comparable technology. You want to be able to detect at lower signal to noise ratios (SNRs) while minimizing the beam dwell and the transmitter power of your radar.
The modern airspace today includes advanced fourth- and fifth-generation aircraft which have more maneuverable and lower radar cross section. Unmanned air vehicles and unmanned combat air vehicles are also inherently smaller and harder to detect and track. Detection of small targets in the presence of noise and clutter interference presents a formidable task in a radar system design.
The linear dynamic range of RF receivers is a limiting factor in the performance of high-end military radar receiver. The nonlinear distortion generated in the ADC and the analog receiver limits the capability of the backend radar signal processor.
The next generation of ADC from major vendors is expected to provide 300 Ms/sec with 16-bit resolution. In the commercial world, the status quo is 14-bit resolution, but in many military systems 10-12 bit is pushing and numerous new radar are only using 10 bits, as discussed in Military Embedded Magazine.
Those extra few dBs of resolution will enable receivers, such as radars and Radar Warning Receivers, to perform more effectively. Electronic intelligence (ELINT) equipment can take advantage of the improved resolution to perform single emitter identification more accurately and at greater range. The Electronic Countermeasures world will be able to detect targets earlier and react quickly to encountered threats, thereby improving the Probability of Survival.
In any digitization process, the faster the signal is sampled, the lower the noise floor.
The faster a signal is sampled, the lower the noise floor because the noise is spread over more frequencies. The noise floor (referenced to the full scale value of the ADC) is: Noise Floor (dBFS) = 6.02 * Bits + 1.76 + 10 Log (Fs/2).
SNR of the ADC may be greatly improved by filtering just the bandwidth of the desired signal. Therefore, the SNR is proportional to 10 Log (Fs/Filter BW). The greater the ratio between sample rate and filter bandwidth, the higher the SNR.
Dynamic range is critical to increased radar performance, especially in the case of passive target detection using signals of opportunity. Transmitting any RF energy is dangerous in a modern threat environment, so passive technology is becoming an emerging technology for airborne radars. Here dynamic range alone is critical in order to separate the much weaker reflected signal from the direct path broadcast signal of opportunity.
Various techniques can be implemented to improve the sampling rate beyond the capability of a single ADC semiconductor. Many techniques, such as interleaving ADCs, stacked ADCs, and the use of nonlinear gain stage, were tried years ago and have not been researched in the current environment of much faster floating point Field Programmable Gate Arrays (FPGAs), mezzanine cards, faster data busses, and much faster multicore, parallel processors.
Interleaving ADCs and synchronizing them should be easier today given the speed and gate count of modern FPGAs. Many of these other techniques were tried in the past because nothing else worked. Today, we need to explore what can be done to maximize the sample rate, dynamic range, and upgradeability for modern airborne radars up against the new emerging threats.
PHASE I: Quantify the theoretical dependencies of ADC sample rate and dynamic range on resolution, SNR, gain, and tracking ability in various radar configurations. Evaluate sampling multiple times per pulse using various waveforms and the impact on single pulse Doppler determination, cross-correlation, unambiguous range, de-ghosting, multi-path discrimination, and electronic protection.
PHASE II: Develop parameter assessment tool which helps acquisition community predict performance. Assess which sampling techniques for transmitted and received waveforms are compatible with various radar architectures. Evaluate various acquisition board architectures which can keep pace with bandwidth and sample rate improvements. Recommend novel architecture designs which will allow rapid insertion of faster ADC, data bus, and processor technology taking into account SWAP-C for airborne radar.
PHASE III DUAL USE APPLICATIONS: Construct a prototype system (hardware and analysis software) and validate in production representative environment. Follow-on activities include specific application integration and creation of any customer-unique requirements and documentation. Develop commercialization plan and market analysis.