DARPA RTRA developing array processors reconfigurable with missions

All modern personal computers including desktops, notebooks, smartphones, and tablets, are examples of general-purpose computers. General-purpose computing incorporates ‘Von Neumann’ approach, which states that an instruction fetch and a data operation cannot occur simultaneously. Therefore, being sequential machines, their performance is also limited.

On the other hand, we have the Application Specific Integrated Circuits (ASICs) which are customized for a particular task like a digital voice recorder or a high-efficiency Bitcoin miner. An ASIC uses a spatial approach to implement only one application and provides maximum performance. However, it can’t be used for the tasks other than those for which it has been originally designed. FPGAs act as a middle ground between these two architectural paradigms.

Unlike conventional chips, programmable hardware whose sub-system configurations can be modified even after fabrication falls under the category of Reconfigurable System. Reconfigurable computing allows designers to harness the power of hardware while still providing the flexibility of software. These systems use Field Programmable Gate Arrays (FPGAs) or similar hardware to accelerate algorithm execution by mapping compute-intensive calculations onto a reconfigurable substrate. These hardware resources are frequently coupled with a general-purpose microprocessor that is responsible for controlling the reconfigurable logic and executing program
code that cannot be efficiently accelerated. The programmable hardware itself can be comprised of one or more commercially available FPGAs, or can be a custom device designed specifically for reconfigurable computing.

Run-time reconfiguration (RTR) expands upon the idea of reconfigurability by providing the ability to change the reconfigurable hardware not only between applications, but also within a single application. Over the course of program execution different configurations can be loaded into the FPGA to perform different hardware-optimized computations at different points in time, essentially providing a method for virtual hardware.

Traditional FPGA structures have primarily been serially programmed single-context devices, allowing only one configuration to be loaded at a time. This type of FPGA is programmed using a serial stream of configuration information, requiring a full reconfiguration if any change is
required. Designers of reconfigurable systems have found this style of configuration to be too limiting to efficiently implement run-time reconfigurable systems.

Using RTR, applications that may not have been able to fit completely onto the fabric can be partitioned and executed on this virtual hardware. This potentially allows a larger percentage of a program to be accelerated in hardware than could be accelerated without RTR, increasing the benefits of runtime reconfiguration. However, the cost of reconfiguration can be quite high. In some situations, configuration overhead can comprise over 98.5% of execution time. This amount of overhead has the potential to eclipse the benefits gained through use of the reconfigurable hardware in RTR applications. Therefore, in order to reap the benefits of RTR, it is essential to minimize configuration overheads.

RTRAs combines the high performance and power efficiency of application-specific integrated circuits (ASICs) with the flexibility and reprogrammability of field programmable gate arrays (FPGAs). These architectures potentially offer significant benefits for streaming signal processing and other applications, particularly when systems must operate in uncertain environments whose characteristics are difficult to specify at design time.

In modern warfare, decisions are driven by information. That information can come in the form of thousands of sensors providing information, surveillance, and reconnaissance (ISR) data; logistics/supply-chain and personnel performance measurements; or a host of other sources and formats. The ability to exploit this data to understand and predict the world around us is an asymmetric advantage for the Department of Defense (DoD).

RTRAs potentially offer the ability to:

• Address a much broader set of applications and environments relative to ASICs at
  lower development costs and timelines
• Outperform the processing throughput of FPGAs by one or more orders of magnitude
  while retaining high input/output (I/O) bandwidth and low latency
• Deliver dramatically shortened compilation times relative to FPGA workflows
•  Achieve far faster reconfiguration times, moving from millisecond to microsecond or
  nanosecond timescales

These benefits open new possibilities to improve decision-making at the tactical edge, enabling these systems to reason over the glut of sensor data while satisfying relevant size, weight, power, and cost (SWaP-C) constraints.

Examples include real-time mode switching for multifunction sensors and processing pipelines that self-optimize to dynamic environments. Realizing these benefits requires overcoming multiple hardware and software challenges, including managing the flow of programming data throughout the processing array, programming models and tools that account for spatial and temporal dynamism, and data-driven run-time scheduling of highly parallelized compute resources.

Request for Information responses from Defense Advanced Research Projects Agency’s (DARPA) Microsystems Technology Office (MTO) seeks information on run-time reconfigurable array (RTRA) processors and novel DoD applications enabled by these architectures by Feb 2022. Of particular interest are RTRAs that can reconfigure their processing pipelines during program execution in fewer than 100 clock cycles. The goal of this Request for Information (RFI) is to assess the state of the art of RTRAs, identify DoD capabilities that could take advantage of these devices, and identify key challenges and opportunities to inform potential future research programs.

Topic 1, Runtime Reconfigurable Architectures: Processors and corresponding software architectures that support reconfiguration in fewer than 100 clock cycles are of interest. Architectures that enable real-time adaptation of streaming data processing in dynamic environments are of particular interest. Processing elements in these architectures may be heterogeneous or homogeneous and either coarse- or finegrained.

Topic 2, Defense Applications: RF, signal processing, and edge autonomy applications are of particular interest but any applications that would significantly benefit from runtime reconfigurable architectures are in scope. Applications may be defense only or dual-use.