The wide adoption of smartphones, high-definition content streamed on social media, the Internet of Things, data saved to the cloud, and artificial intelligence used in massive data analytics have ushered in the current era of digital economies and Industry 4.0. These applications demand high-bandwidth optical networks and digital infrastructures capable of massive data processing. As a result of these demands, there has been an emergence worldwide of hyperscale data centers and 5G access networks.
Today, CMOS nano electronics integrated circuits comprise the majority of information processing systems. Silicon has long been the primary material to develop microelectronic circuits due to its unmatched electronic, mechanical and thermal properties and its abundance on earth’s crust (27.7%). Accordingly, the semiconductor industry, and the Complementary Metal-Oxide Semiconductor (CMOS) technology in particular, has experienced astounding progress in the last 60 years since the first demonstration of a working silicon integrated circuit.
Nowadays, the world’s largest CMOS foundries race towards the implementation of ever-smaller technology nodes to increase the density of transistors-per-chip and, thereby, be able to sustain the massive data traffic demand of our modern hyper-connected society. But improvements in efficiency of conventional electronic data systems cannot catch up with the soaring data traffic, which calls for the integration of photonic functionalities onto the conventional Si-based electronic platform. The integration could produce optoelectronic integrated circuits with unparalleled speed and functionalities, and enable new applications. Yet fundamental differences between Si and III-V materials means it is extremely challenging to directly grow III-V functionalities on the Si-platform.
Traditionally, optical fiber telecom networks were long-distance information carriers wherein III-V semiconductor-based optoelectronics components such as laser diodes and photodetectors were key devices in optotransceivers. Despite significant research efforts and a major investment, we are rapidly approaching important physical limitations, such as the impossibility to scale down the copper interconnects to the same extent as microelectronic devices. The demand for high interconnect bandwidth in hyperscale data centers and access networks has brought about the replacement of copper-based system interconnects with optical interconnects.
Silicon photonics has emerged as a disruptive technology to address interconnect and data bottlenecks inside of systems and between computing components, enhancing power efficiency, improving response times and delivering faster insights from Big Data. It offers a virtually unlimited optical bandwidth, large scalability, inexpensiveness and an efficient compact on-chip routing that goes beyond the scope of any other technology to date. The major advantages of SiPh are the potential to integrate optical and electronic devices within the same IC and its compatibility with the existing complementary metal-oxide semiconductor process (CMOS) for fabrication.
Silicon photonics refers to the application of photonic systems using silicon as a medium for optical signal transmission . The silicon material used in such photonic systems is designed with sub micrometer precision and is deployed into the microphotonic components. Silicon photonics combines technologies such as complementary metal oxide semiconductor (CMOS), micro-electro-mechanical systems (MEMS) and 3D Stacking.
Wide-spread adoption of silicon photonics has been hampered in part by the lack of monolithically integrated laser sources. Whilst there has been a range of microminiature lasers incorporated directly into silicon over the years, including melding germanium-tin lasers with a silicon substrate and using gallium-arsenide (GaAs) to grow laser nanowires, these methods have involved compromise.
The ultimate physical manifestation of the silicon photonic device would be as part of an optoelectronic integrated circuit (OEIC) formed monolithically in silicon, combining the photonic functionality and the electronic intelligence in seamless integration. This requires realization of integrated photonic circuits that integrates a laser source, couplers, power dividers, modulators, optical multiplexer/demultiplexers, phase rotators, and attenuators giving a designer the ability to create the entire transmit and receive optical system within a single IC. The number of assembly steps are dramatically reduced with SiPh devices and, therefore, so is manufacturing time and production cost.
Heterogeneous and Hybrid Integration
Optoelectronic industry designers have traditionally used discrete optical devices for transceiver designs. The process requires manual integration of discrete free-space optical components such as lasers, modulator, photo detectors, isolators, MUX/DE-MUX, lenses in the form of optical gold box sub-assemblies such as transmit optical sub-assembly (TOSA) and receive optical subassembly (ROSA). The TOSA and ROSA assembly process is quite restrictive and expensive because it may require multiple active and passive optical alignments during manufacturing e.g., laser to modulator, modulator to optical multiplexer, and de-multiplexer to photodiode etc., which makes the entire assembly process quite cumbersome. Due to the manual nature of the assembly process, it limits high volume manufacturing and the product ramp is usually difficult.
Furthermore, the implementation of Si photonic integrated circuits (PICs) is naturally endorsed by the large refractive index contrast between silicon (n = 3.45) and its native oxide (n = 1.45). Thus, the silicon-on-insulator (SOI) technology has become the flagship platform for large-scale silicon photonics, placing it at a mature stage of development with many standalone off-the-shelf optical and optoelectronic components.
Silicon shows satisfactory performance as light receiver, but, due to the indirect bandgap nature, the widely used silicon CMOS is very inefficient at light emitting. This feature of its electronic structure, according to the laws of quantum mechanics, strictly speaking, prohibits the emission of light (luminescence) under external excitation. The integration on silicon of efficient indium phosphide based light sources, currently driving long-range telecommunication networks, is known to be very challenging, owing to the large mismatch in crystal lattice constants between both materials.
The two main approaches have been pursued, which are often referred to as heterogeneous integration and hybrid integration. In the short term, the most competitive strategy is the heterogeneous integration of III-V materials onto silicon to exploit the best characteristics from each material set. An intuitive way to match both technologies is the direct assembly of independently processed SOI and III-V chips by using either direct mounting of stacked chips (flip-chip integration) or in-plane butt-joint coupling technique
Heterogenous integration is based on bonding of unpatterned III–V dies onto pre-processed silicon photonic (SiP) wafers such that light generated in the epitaxial layers of the III–V die is evanescently coupled to the SiP waveguides . III-V devices are then fabricated by wafer-scale processing of the dies, where all structures are lithographically aligned with highest precision.
High-precision positioning of dies is hence not necessary – a key advantage compared to hybrid integration. However, while heterogeneous integration is particularly well suited for large-scale mass fabrication of III-V light sources on SiP circuits, the associated technical complexity is still considerable, in particular with respect to the stringent requirements of ultraclean and extremely smooth surfaces. Moreover, heterogeneously integrated light sources may consume considerable real estate on the SiP chip, and heat-sinking is challenging due to the high thermal resistance introduced by the III-V-to-silicon bonding layer and by the buried oxide.
In spite of this constraint, flip-chip integration is currently being used by several technology corporations when low-volume silicon photonics solutions are required
Hybrid integration, in contrast, relies on optically connecting readily processed III-V lasers , gain chips, or even photodiodes to silicon photonic (SiP) circuits, where the III-V device may either be mounted on top of the silicon substrate or next to it. Hybrid integration maintains the superior performance characteristics of native III-V light sources and allows for testing of devices prior to system assembly, but comes with fabrication challenges.
In particular, efficient optical coupling of the III-V to the SiP waveguides usually relies on alignment with precisions in the lower micrometer or even sub-μm range. This often requires slow and expensive active alignment techniques, where the coupling efficiency is continuously monitored while optimizing the position of the devices .
Moreover, additional devices such as micro-lenses, prisms, or micro-mechanical carriers are needed to adapt the mode field size and the emission direction of the III-V light source to that of the SiP circuit, leading to comparatively big assemblies. In many cases, the III-V devices are mounted on top of the SiP die. This approach does not only consume substantial on-chip real estate, but also poses challenges with respect to heat-sinking of the III-V devices through the underlying silicon-on-insulator (SOI) substrate due to the relatively poor heat conductivity of the buried oxide. In hybrid integration, optical coupling losses of 2.3 dB have been previously demonstrated for butt coupling of a III-V laser diode array to an array of SiP waveguides equipped with trident spot-size converters that relax alignment tolerances to ± 0.7 μm.
External versus direct heterogeneously integrated lasers
The most common laser used in photonics links is an InP based chip laser that is separate (external) from the silicon photonic IC. The laser is packaged either in traditional single mode packages like TO-cans or in silicon based micropackage.
Imec and Ghent University have for the first time monolithically integrated arrays of indium phosphide lasers on 300mm silicon substrates in a CMOS pilot line. Lasing operation was demonstrated for all tested devices consisting of an array of ten indium phosphide lasers. Typical lasing threshold powers of around 20mW were observed at room temperature under optical pumping.
One of the important goals of silicon photonics is the realization of practical silicon lasers. An optically-pumped Raman silicon laser is a bulk silicon laser capable of room-temperature continuous-wave (cw) operation. Japanese researchers from Osaka Prefecture University and Kyoto University developed Microwatt-Threshold continuous-wave Raman silicon laser using a photonic-crystal high-Q nanocavity.
A team of collaborating scientists from Hong Kong University of Science and Technology, the University of California, Santa Barbara, Sandia National Laboratories and Harvard University have found a way to create microscopically-small lasers directly from silicon, unlocking the possibilities of direct integration of photonics on silicon and taking a significant step towards light-based computers.
“Our lasers have a very low threshold and match the sizes needed to integrate them onto a microprocessor, and these tiny high-performance lasers can be grown directly on silicon wafers, which is what most integrated circuits (semiconductor chips) are fabricated with,” said professor Kei May Lau, Department of Electronic and Computer Engineering, Hong Kong University of Science and Technology.
Researchers first had to find a way to refine silicon crystal lattices so that their inherent defects were reduced significantly enough to match the smooth properties found in GaAs substrate lasers. They did this by etching nano-patterns directly onto the silicon to confine the defects and ensure the necessary quantum confinement of electrons within quantum dots grown on this template.
The researchers were then able to use optical pumping, which is a process in which light is used to raise or “pump” electrons from a lower energy level to a higher one, to demonstrate that the devices they created were able to operate as lasers.The next step for this research, according to Lau, is to see if it is possible to create electrically-pumped lasers using standard microelectronics technology
Researchers from the University of California, Santa Barbara have managed to place billions of light-emitting dots, or “quantum dots,” directly onto silicon, allowing lasers and other components to be easily integrated into silicon, paving the way for advanced photonic integrated circuits with far more functionality than can be achieved today.
The work was sponsored by Defense Advanced Research Projects Agency under their Electronic-Photonic Heterogeneous Integration. E-PHI program was set out in 2011 to develop technologies and architectures to enable chip-scale electronic-photonic / mixed-signal integrated circuits on a common silicon substrate.
First bufferless 1.5 μm III-V lasers grown directly on silicon wafers in Si-photonics
Researchers from the Hong Kong University of Science and Technology (HKUST) have reported the world’s first 1.5 μm III-V lasers directly grown on the industry-standard 220 nm SOI (silicon-on-insulators) wafers without buffer, potentially paving an opening to the “holy grail” for present silicon (Si-) photonics research.
Seamlessly bridging the active III-V light sources with the passive Si-based photonic devices, the demonstration could be deployed as light sources in integrated circuits to greatly improve circuit speed, power efficiency and cost-effectiveness. In other conventional approaches of integrating III-V lasers on Si in the literature, thick III-V buffers up to a few micrometers are used to reduce the defect densities, which posts huge challenges for efficient light interfacing between the epitaxial III-V lasers and the Si-based waveguides.
For the first time in history, the research team led by Prof. Lau Kei-May of HKUST’s Department of Electronic and Computer Engineering and Post-doctoral Fellow Dr. Han Yu devised a novel growth scheme to eliminate the requirement of thick III-V buffers and thus promoted efficient light coupling into the Si-waveguides. The bufferless feature points to a fully integrated Si-based photonic integrated circuits. That has enabled the first demonstration of 1.5 μm III-V lasers directly grown on the industry-standard 220 nm SOI wafers using metal organic chemical vapor deposition (MOCVD). Previous demonstrations required non-industry-standard bulk Si or thick SOI wafers. The research findings were recently published online in Optica in February 2020.
Russian scientists demonstrate ion implantation advantages for the use of silicon in optoelectronics
Silicon shows satisfactory performance as light receiver, but, due to the indirect bandgap nature, the widely used silicon CMOS is very inefficient at light emitting. This feature of its electronic structure, according to the laws of quantum mechanics, strictly speaking, prohibits the emission of light (luminescence) under external excitation. “It would be very undesirable to refuse from silicon at a new stage, as we would have to abandon the perfectly developed technology for mass production of integrated circuits. This would involve huge material costs, not to mention the environmental problems that arise when working with A3B5 materials,” states Professor David Tetelbaum, Leading Researcher at Lobachevsky University.
Scientists are trying to find a way out of this situation by either using nanocrystalline silicon, or by coating silicon with films of other light-emitting materials. However, the emissivity (luminescence efficiency) of silicon nanocrystals is still insufficient for practical applications. Besides, silicon nanocrystals emit in the area at the “red” edge of visible radiation, while many technical applications, in particular in fiber optics communication technology, require longer wavelengths (about 1.5 μm). The use of “foreign” material layers on silicon substrates, however, is poorly compatible with the traditional silicon technology.
An effective way to solve this problem is to introduce in silicon a special type of linear defects known as dislocations. Researchers have come to the conclusion that a high concentration of dislocations can be achieved in the silicon surface layer by irradiating it with silicon ions with the energy of the order of a hundred keV and then annealing it at high temperatures. In this case, silicon emits light at exactly the right wavelength – close to 1.5 μm. “The luminescence intensity appears to depend on the implantation and annealing conditions. However, the main problem with dislocation-related luminescence is that it is most pronounced at low temperatures (below ~25 K) and decays quickly as the temperature rises. Therefore, it is very important to find ways to increase the thermal stability of dislocation-related luminescence”, continues Alexey Mikhaylov.
Lobachevsky University scientists together with their colleagues from the RAS Institute of Solid State Physics (Chernogolovka) and the Alekseev State Technical University (Nizhny Novgorod) have made significant headway in solving this problem with the support of the Russian Foundation for Basic Research (grant No.17-02-01070).
Previously, it was found that one way to achieve dislocation-related photoluminescence in silicon samples is to implant silicon ions into silicon (self-implantation) with subsequent annealing. This proved to be not the only benefit of the implantation technology, when the team of Lobachevsky University discovered that additional boron ion doping can enhance the luminescence. However, the phenomenon of enhanced luminescence properties alone does not solve the main problem. Moreover, it remained unclear how boron ion doping affects the luminescence thermal stability, which is a key parameter, and under what conditions (if any) such effect will be most pronounced.
In this study, scientists have confirmed experimentally the increase in thermal stability of silicon doped with boron ions. Moreover, the effect is nonmonotonically dependent on the boron dose, and in a certain range of doses, a pronounced second maximum in the region of 90 to 100 K appears on the intensity versus temperature curve, along with the usual low-temperature maximum in the region of 20 K. “It is important to note that the “beneficial” effect of boron is unique in the sense that the replacement of boron ions by another acceptor impurity does not lead to the effect described above. After refining the modes of boron ion doping and heat treatment of silicon samples where centers of dislocation-related luminescence were formed by irradiation with silicon ions, we have found that with the highest previously used dose of boron ions and an additional heat treatment at 830° C, it is possible to achieve a measurable level of luminescence at room temperature,” concludes Professor Tetelbaum. The results obtained during further optimization of the implantation and heat treatment conditions brighten up the prospects for silicon application in optoelectronics.