Microelectronics are essential to technology competition in economic and national security realms. Microelectronics are designated a critical national security technology and foundational for other critical and emerging dual-use technologies such as advanced computing, artificial intelligence, autonomous systems and robotics, communications and networking, and networked sensing. Recent experience with supply chain disruptions from the COVID-19 pandemic and a rapidly shifting geopolitical order have reassessed domestic capabilities for manufacturing microelectronics for continued U.S. leadership.
While silicon transistor scaling will continue over the next decade, traditional technology scaling alone will provide diminishing cost and performance improvements and is unlikely to drive future long-term microelectronics innovation. Access to leading edge-silicon, while critical, must be regarded as one element of a longer-term view of advanced capabilities and supply chain security. This longer view needs to address the next wave of innovation that will overtake the role that complementary metal oxide semiconductor (CMOS) transistor scaling held until now.
The next major wave of microelectronics innovation is expected to come from the ability to integrate heterogeneous materials, devices, and circuits through advanced packaging, producing a tightly coupled system that extends into the third dimension with performance that exceeds what is available from today’s monolithic approach. This was echoed by a recent statement, “As we enter the advanced packaging era, these 2D (two-dimensional) and 3D stacking technologies give architects and designers the tools to further increase the number of transistors per
The 2019 Institute of Electrical and Electronics Engineers (IEEE) Heterogeneous Integration Roadmap states “Heterogeneous Integration refers to the integration of separately manufactured components into a higher-level assembly (System in Package – SiP) that, in the aggregate, provides enhanced functionality and improved operating characteristics.” The 3D part of 3DHI refers to stacking these components on each other within the same package.
While industry leaders such as Advanced Micro Devices (AMD), Intel, and Micron Technology in the U.S., Samsung and SK hynix in South Korea, and Taiwan Semiconductor Manufacturing Corporation (TSMC) in Taiwan have aggressively pursued advanced packaging for logic and memory, their advances may not widely benefit the U.S. domestic semiconductor industry without new strategies for pre-competitive collaboration and the development and adoption of 3DHI technologies and standards, says DARPA.
Barriers in the current U.S. ecosystem that limit or slow the progress in 3DHI R&D include:
• lack of centralized facilities to facilitate information sharing during development
• lack of common standards
• lack of access to affordable manufacturing capacity for low-volume products
o very long iteration cycles at existing facilities
o expensive fabrication equipment
• limitations of expensive and proprietary design tools for exploring new concepts.
Presently, the U.S. has no open-access manufacturing center with comprehensive capacity for 3DHI research and development. With very few exceptions, U.S. companies engaged in 3DHI research rely upon off-shore facilities, e.g., TSMC (Taiwan) and Interuniversity Microelectronics Center (IMEC, Belgium). An open-access national manufacturing center for 3DHI R&D would result in a more expansive wave of innovation, would promote shared
learning, and would ensure that start-ups, academia, and the defense industrial base could engage in 3DHI R&D for low-volume products.
In the William M. (Mac) Thornberry National Defense Authorization Act (NDAA) for Fiscal Year (FY) 2021 (Public Law 116-283), Congress authorized multiple federal agencies to create public-private partnerships to promote domestic manufacturing research capacity in the microelectronics sector. Notably, Congress directed the Department of Commerce, in collaboration with the Department of Defense, to establish a National Semiconductor
Technology Center to “conduct research and prototyping of advanced semiconductor technology to strengthen the economic competitiveness and security of the domestic supply chain,” and a National Advanced Packaging Manufacturing Program “to strengthen semiconductor advanced test, assembly, and packaging capability in the domestic ecosystem.”
Modern warfare is increasingly dependent on microelectronics capabilities that sense the environment, convert the signals into data streams, process the information, and generate a response. In this sense, Aerospace and Defense (A-D) systems are quite similar to commercial systems that perform communications and computations, while taking advantage of the advancement of semiconductor density, functionality, and cost reduction due to Moore’s Law. There is the everincreased demand for more data throughput through wired and wireless systems. Cellular systems have migrated from 3G to 4G and now 5G architectures which improves bandwidth ~10X with each generation. DoD systems for communications, radar, and sensing generally require wider bandwidths, higher dynamic range, and higher transmit power, as well as specialized frequency bands and security requirements that the commercial side does not require.
The Department of Defense is also directed to establish a National Network for Microelectronics Research and Development (NNMRD) composed of United States research universities to enable the laboratory-to-fabrication transition of microelectronics innovations. This network, which will be established by the Under Secretary
of Defense for Research & Engineering (USD(R&E)), is referred to as the “Microelectronics Commons” or “the Commons.” It is expected that the Commons will consist of multiple regional, university-focused U.S. innovation hubs to foster a pipeline of ideas and talent from university labs and small business teams across a wide range of device technologies and circuit architectures. While these new efforts will foster innovation broadly, neither specifically addresses the need for an open-access, national manufacturing center for 3DHI R&D.
Industry leaders currently use 3D integration of modestly dissimilar silicon digital technologies for a narrow range of commercial products, from stacked dynamic random access memory (DRAM) to CMOS imagers to high-performance computing. However, the opportunity to broadly impact defense systems relies on expanding the types of microelectronics that can be integrated and assembled. Today’s mature integration techniques, even those often referred to as 3DHI, focus primarily on lowpower, leading-edge CMOS, legacy CMOS, and silicon-based memory. Advancing digital integration requires increasing interconnect densities well beyond today’s state-of-the-art.
Anticipating that the next major wave of microelectronics innovation will come from the ability to integrate heterogeneous materials, devices, and circuits through advanced packaging, DARPA is proposing to stand up a national accelerator specifically for next-generation 3DHI. This national accelerator would take the form of a pilot-line manufacturing capability that would allow users from across the country to assemble and test their R&D designs without the need for expensive investments in their own capability. This national accelerator would be distinguished from the other congressionally authorized efforts by its emphasis on the heterogeneous integration of multiple material systems, rather than prioritizing only silicon-based technologies.
In addition, the accelerator will employ a holistic approach to specifically advance domestic 3DHI capabilities. This national accelerator would prioritize:
• centralized manufacturing resources;
• short turn-around manufacturing process cycle times; and
• cost-effectiveness from shared resources for design, packaging, assembly, and testing.
The Next-Generation Microelectronics Manufacturing (NGMM) program seeks to establish a holistic domestic capability for 3DHI R&D, developing key process modules for the design, packaging, assembly, and testing of 3DHI microsystems. If successful, the program will provide:
• an open-access manufacturing center to holistically address design, assembly, packaging, and testing;
• a pilot-line manufacturing capability;
• multi-project runs or dedicated taxi runs as a feature of the research service; and
• training and orientation for all users.
DARPA’s August 2022 solicitation of Next-Generation Microelectronics Manufacturing (NGMM) focuses on 3DHI stacking of separately manufactured components from different material systems, within a single package, to produce a microsystem that provides revolutionary improvements in functionality and performance.
DARPA’s expansion to heterogeneous integration also includes compound semiconductors for radio frequency (RF) and photonics for interconnect, novel memory devices for computing, and wide-bandgap and ultra-wide bandgap semiconductors for power electronics.
The 3D heterogeneous integration (3DHI) of high power and efficiency Gallium Nitride (GaN) power amplifiers (PAs) with functionally dense Si CMOS (complementary metal-oxide-semiconductor) logic will create a new class of compact, digitally enhanced RF integrated circuits (ICs) that will revolutionize radar and multifunction systems.
NGMM Program Structure
Phase 0 of NGMM is a 6-month, single phase effort that seeks to provide a detailed analysis to define a 3DHI manufacturing center between the United States Government (USG), academia, and industry. Phase 0 of this program, which is the focus of this BAA, will inform planning for the manufacturing center by defining exemplar 3DHI microsystems and identifying the equipment, processes, software tools, and facility requirements for manufacturing these microsystems. This initial phase will emphasize defining the requirements and capabilities of a 3DHI R&D/prototyping ecosystem rather than solving a specific design challenge. DARPA expects that performers will leverage existing designs that would benefit from 3DHI architecture.
Proposers will provide a detailed analysis of an exemplar 3DHI microsystem . In Phase 0, DARPA encourages proposers to form teams consisting of, but not limited to, microsystem designers, tooling manufacturers, and system integrators. In addition to the analysis of the exemplar 3DHI microsystem, proposers will provide specific recommendations for the software and hardware tools needed to manufacture their microsystem, including, but not limited to, electronic design automation (EDA) tools, packaging and assembly tools, and metrology and test tools and techniques.
The output of Phase 0 will be a detailed analytical report of exemplar 3DHI microsystems that could be fabricated in the 3DHI manufacturing center. In addition to providing a description of the layout, performance benefits, and applications, the report will describe the required equipment and process modules for manufacturing and testing the 3DHI microsystem.
Another goal of Phase 0 is to determine an operational balance in the diversity of the 3DHI processes that will be supported in the 3DHI manufacturing center. DARPA recognizes that too narrow a selection of processes may not prove useful to the targeted set of users (academia, defense industrial base, small businesses), while too broad a set may be prohibitively expensive and time-consuming to develop and sustain.
Phases 1 and 2 will focus on establishing the 3DHI manufacturing center, creating and finalizing baseline process modules, qualifying the pilot-line manufacturing process, and implementing the R&D access model for the center.
Exemplar Microsystems and Process Modules
For this solicitation, NGMM aims to emphasize 3DHI microsystems that incorporate different material systems in the same package, such as photonics for interconnects, novel memory devices for computing, and wide-bandgap and ultra-wide bandgap semiconductors for power electronics, and additively manufactured passive components. Specifically, Phase 0 of NGMM seeks to define disruptive representative microsystems that integrate disparate wafers or chips into vertically stacked architectures.
It is expected that the microsystems defined in this research study will reflect significant advances in the state-of-the-art for 3DHI performance and packaging by innovating in areas such as architecture, integration approach, novel materials, thermal and power management, and interconnect density.
The exemplar microsystems should have a minimum of three individual 2D chips vertically integrated together. In addition, they should contain a minimum of two disparate semiconductor material systems, such as Si, SiGe, GaAs, GaN, InP, HgCdTe, SiC, etc., rather than just two different Si CMOS technology nodes (e.g. 7 nm and 22 nm); however, deeply scaled CMOS as a part of the microsystem is not excluded.
It is expected that the 3DHI microsystems fabricated within the 3DHI manufacturing center will comprise wafers, die, or chips that originate from multiple external foundries, laboratories, and process technologies, and are assembled using leading-edge packaging solutions. Incorporating diverse sets of die into a single, manufacturable package will require design standards to ensure successful integration. Proposers should address any needs for interface standards for chips that originate in different facilities and contain different semiconductors, metals, and dielectrics. For example, the integration of a GaN power amplifier with a silicon digital circuit may require
reconciling dissimilarities in design and materials.