DARPA ERI developing breakthrough U.S. national electronics capability for DOD missions to secure its national security

Rajesh Uppal June 15, 2023 Doctrine & Strategy, Electronics & EW, Industry Comments Off on DARPA ERI developing breakthrough U.S. national electronics capability for DOD missions to secure its national security 1,143 Views

In 1965 R&D Director at Fairchild (and later Intel co-founder) Gordon Moore predicted continued systemic declines in cost and increase in performance of integrated circuits in his paper “Cramming more components onto integrated circuits.” These trends have underwritten the ongoing microelectronics revolution. “Moore’s Law has set the technology community on a quest for continued scaling and those who have mastered the technology to date have enjoyed the greatest commercial benefits and the greatest gains in defense capabilities,” said Chappell.

Moore’s Law still applies, but the design work and fabrication now required to keep on pace is becoming ever more difficult and expensive. “The current trajectory is straining commercial and defense developments,” said Chappell. We’ve got underlying trends where the physics is already hard and getting harder. And that’s expressing itself in the cost across the board, whether that’s design, manufacturing, or even writing the software on top of a system-on-chip. Most aspects of electronics are getting more expensive, and larger design teams are needed to manage the underlying complexity.

That has consequences across commercial industry and across the defense industry. In June 2017, DARPA Microsystems Technology Office (MTO) announced a new five-year, upwards of $1.5B investment Electronics Resurgence Initiative (ERI) to ensure far-reaching improvements in electronics performance well beyond the limits of traditional scaling

Each wave of modern electronics development has benefitted from the combination of defense-funded academic research and commercial sector investment. In the 1980s, when geometric silicon scaling started to make low-volume integrated circuit fabrication unaffordable, DARPA’s investment in the Metal Oxide Silicon Implementation Service (MOSIS) opened the door to rapid, low-cost chip manufacture, laying the foundation for the nation’s world-leading fabless design industry.

In the 1990s, a combination of defense, academic, and commercial partners pioneered 193nm lithography, which became the industry critical fabrication process over the past two decades. A third wave of electronics innovation emerged as Dennard scaling ended in the 2000s, with the semiconductor industry adopting Fin Field Effect Transistors (FinFETs), a DARPA-funded innovation that drove low power computing and kicked off an era of 3D devices.

Building on the tradition of other successful government-industry partnerships, ERI aims to forge forward-looking collaborations among the commercial electronics community, defense industrial base, university researchers, and the DoD to address these challenges.

According to DARPA DOD’s greatest technical challenges are intrinsically “dual-use” ones that depend on and demand working with industry. Our national security cannot not be assured without a strong domestic microelectronics industry. There has been the convergence of the goals and concerns of DoD with that of the US industrial base.

In modern warfare, decisions are driven by information coming from, for example, thousands of sensors providing ISR (intelligence, surveillance, and reconnaissance) data, logistics/supply-chain data, and personnel performance measurements. “Utilization of this data relies on computational algorithms running at huge scale,” according to the BAA. Next-generation intelligent systems supporting Department of Defense (DoD) applications in artificial intelligence, autonomous vehicles, shared spectrum communication, electronic warfare, and radar will require processing efficiency orders of magnitude better than what is offered by current commercial electronics.

Reaching the performance levels required by our Nation’s needs will require development of highly complex SoC platforms leveraging the most advanced integrated circuit technologies. Unfortunately, as the complexity of chips has rapidly increased in line with Moore’s law predictions, recent years have seen an explosion in the cost and time required to design advanced SoCs, PCBs, and SiPs.

NDAA authorizes new models to support innovation and access

According to FY21 NDAA, The DoD may establish a national network for microelectronics research and development— (A) to enable the laboratory to fabrication transition of microelectronics innovations in the United States; and (B) to expand the global leadership in microelectronics of the United States.

The DoD (including DARPA) shall deliver –

(14) A plan for increasing commercialization of intellectual property developed by the Department of Defense…
(15) An assessment of the feasibility, usefulness, efficacy, and cost of (A) developing a national laboratory exclusively focused on the research and development of microelectronics… and (B) incorporating…access to funding resources, fabrication facilities, design tools, and shared
intellectual property [for early-stage microelectronics startups]…
(16) The development of multiple models of public-private partnerships to execute the strategy, including in-depth analysis of establishing a semiconductor manufacturing corporation…

DARPA ERI program

In June 2017,DARPA announced the Electronics Resurgence Initiative (ERI) as a bold response to several technical and economic trends in the microelectronics sector. Among these trends, the rapid increase in the cost and complexity of advanced microelectronics design and manufacture is challenging a half-century of progress under Moore’s Law, prompting a need for alternative approaches to traditional transistor scaling. Meanwhile, non-market foreign forces are working to shift the electronics innovation engine overseas and cost-driven foundry consolidation has limited Department of Defense (DoD) access to leading-edge electronics, challenging U.S. economic and security advantages. Moreover, highly publicized challenges to the nation’s digital backbone are fostering a new appreciation for electronics security—a longtime defense concern.

The ERI will draw on new and existing DARPA programs to make a significant investment into enabling circuit specialization and managing complexity. The foundation for the Initiative has been building for a number of years in the form of existing MTO programs such as DAHI, CHIPS and CRAFT, which address ERI’s three research pillars: materials and integration, circuit design, and systems architecture. Another major ERI component is the extensive university-based program—the Joint University Microelectronics Program (JUMP)—that MTO and corporate partners have organized to build up a fundamental research base in fields underlying microelectronic technologies. Established by DARPA in 2017, the initiative is comprised of existing programs as well as six new programs – two for each of the three key research thrusts.

In 2018, DARPA launched the second phase of a potential five-year, $1.5B program that aims to advance microelectronics innovation through new microsystem designs, materials and architectures. DARPA said in Nov 2018 the Electronics Resurgence Initiative’s Phase II seeks to address the need to support domestic production options to advance capability development for diverse needs; advance investments in chip security; and demonstrate the resulting technology platforms in defense applications.

“The U.S. electronics industry has provided global leadership in the electronics arena since the invention of the transistor. “Through ERI, DARPA is seeding the foundation of a more robust, secure, and heavily automated electronics industry to move us from an era of generalized hardware to specialized systems,” Bill Chappell, director of DARPA’s microsystems technology office. The first phase of ERI was a major investment into the research and development required to stay competitive by exploring specialization with novel circuit materials, architectures, and designs.

Chappell noted that ERI’s second phase aims to “push us toward a domestic semiconductor manufacturing sector that can implement specialized circuits; demonstrate that those circuits can be trusted through the supply chain and are built with security in mind; and are ultimately available to both DoD and commercial sector users.” DARPA said Phase II aims to develop unique local manufacturing capabilities by studying the addition of alternative and complementary vectors to CMOS scaling through initiatives including the Photonics in the Package for Extreme Scalability program.\

Given today’s cost, complexity, and security challenges, the nation now stands ready to collaboratively innovate the next wave of electronics progress. ERI’s investments are focused on:

increasing information processing density and efficiency,
accelerating innovation in artificial intelligence hardware to make decisions at the edge faster,
overcoming the inherent throughput limits of 2D electronics,
mitigating the skyrocketing costs of electronic design,
overcoming security threats across the entire hardware lifecycle, and
revolutionizing communications (5G and beyond).

DARPA envisions four key areas of development—3D heterogeneous integration, new materials & devices, specialized functions, and design & security—each of which have been central to ERI since its inception.

Leveraging 3D heterogeneous integration, the 4th wave should support continuing electronics progress despite challenges to traditional silicon scaling. This integration will enable innovators to both add new materials and devices to the silicon foundation and create specialized functions precisely designed to meet the diverse needs of the commercial and defense sectors. To manage the complexity of working in three dimensions, the 4th wave will also demand new architectures and design tools that address rising design costs, enable rapid system upgrades, and make security integration a primary design concern.

As a community, ERI partners must ensure that the benefits from ERI’s 20+ DARPA-funded programs differentially accrue to the U.S. commercial and defense base. To achieve this goal, ERI programs incorporate the joint efforts of dozens of academic, commercial, and defense industry researchers and transition partners. While results to date from these collaborations, as highlighted at the 2018 and 2019 ERI Summits, point to several opportunities to promote U.S. microelectronics leadership, DARPA continuously seeks to launch new research efforts and to attract new partners.

DARPA hosted its third Electronics Resurgence Initiative (ERI) Summit and Microsystems Technology Office (MTO) Symposium in August 2020. The 2020 Summit emphasized ongoing and potential transition opportunities for DARPA technologies that address a range of critical Department of Defense (DoD) and commercial modernization priorities, such as 3D heterogeneous integration, autonomy and artificial intelligence, hardware security and cybersecurity, as well as 5G and future radio frequency (RF) communications.

ERI Phase II

ERI Phase II is focusing on developing new types of manufacturing capabilities and crafting a road map for supplying high-performance electronics for the U.S. Department of Defense (DoD) and its commercial partners. ERI Phase II aims to address three key issues raised by the electronics community . These key issues are the need to support domestic manufacturing options and enable them to develop differentiated capabilities for diverse needs; a demand to invest in chip security; and a desire to create new connections between ERI programs as well as to demonstrate the resulting technologies in defense applications.

ERI:DA is one of several potential broad agency announcements under the recently announced second phase of the DARPA Electronics Resurgence Initiative. Goals of the briefings are to introduce industry to the ERI Phase II defense applications; and provide an overview of current ERI programs. The ERI-DA project seeks to develop revolutionary national defense capabilities that capitalize on technologies developed in existing ERI thrusts — namely, the need to support domestic secure chip manufacturing; invest in chip security; and demonstrate new ERI technologies for defense applications.

To create unique and differentiated domestic manufacturing capabilities, ERI Phase II will explore the addition of complementary and alternative vectors to traditional CMOS scaling. The first program in this space is Photonics in the Package for Extreme Scalability (PIPES), which will explore ways to bring the benefits of optical scaling directly to chips. PIPES will also work to establish a domestic ecosystem that facilitates long-term access to these new photonics capabilities for both commercial and DoD users. By significantly reducing the energy demands and challenges associated with moving data across digital microelectronics, the program could reduce the effort required to tie hundreds of GPUs together, and enable massive parallelism capable of supporting current and emerging data-intensive applications like machine learning, large-scale emulation, and advanced sensors.

Together with PIPES, other ERI Phase II investments are designed to ensure the development of novel manufacturing capabilities and support a strategy for the enduring availability of differentiated, high-performance electronics for the DoD and its commercial partners. This is important for the Department because its electronics manufacturing needs are numerous and diverse, and its systems have unique requirements and specific functionality. Although traditional CMOS scaling for digital processing is still an important area of investment, many critical DoD-relevant electronics will likely derive from alternative and complementary vectors. Potential areas of exploration under ERI Phase II include the integration of microelectromechanical systems (MEMS) and radiofrequency (RF) components directly into advanced circuits and semiconductor manufacturing processes. These efforts will build on the existing work in the ERI Materials & Integration research thrust, complementing current ERI programs like FRANC, 3DSoC, and CHIPS.

Potential areas of exploration include enabling the traceability of electronics components – from design to use – and the development of electronics that can enforce protections for security and privacy. Potential ERI Phase II programs will consider the need for assured electronics that incorporate protections from security risks. These efforts will build on ERI’s Design and Architectures research thrusts and leverage existing DARPA programs, such as SSITH that address hardware security and verification challenges.

ERI Phase II will also investigate ways to increase the connections between the various ERI efforts – from fundamental research programs to technology application programs – as well as emerging and future applications of ERI technologies developed across all sectors to defense-specific systems. These connections between programs and end users are key to ERI’s overall success, driving DARPA’s ability to deliver differentiated capabilities to the DoD and its partners. Programs under development should help ensure that the technological advances that derive from ERI will deliver significant impact for national security. Potential areas of exploration include ERI applications in large-scale physical emulation, cognitive RF systems, next-generation satellites, cybersecurity, and beyond.

The 2021 Summit held in Oct 2021, showcased performer technical achievements and demonstrations across ERI’s six major themes relevant to national security and to the larger microelectronics sector.

Defense Advanced Research Projects Agency (DARPA) Photonics in the Package for Extreme Scalability (PIPES) program

PIPES program, intends to expand the use of optical signaling for data transfer. It also aims to insert high-bandwidth photonics inside the packaging of application-specific integrated circuits (ASICs) and field-programmable gate arrays (FPGAs). Bottlenecks and limited performance occur when data moves between optical transceivers and advanced ICs in the electrical domain. Integrating photonic solutions into the microelectronics package, DARPA researchers posited, would remove this limitation and enable new levels of parallel computing.

DARPA selected teams to take on three research areas under the PIPES program: Development and integration of optical signaling technology for next-generation digital microelectronics, with a particular focus on defense applications, creation of technologies and concepts that will lead to even better technical performance, and the exploration of new approaches to signaling that system architects can put into practice.

The PIPES project’s first research area – focused on developing high-performance optical input/output (I/O) technologies packaged with advanced ICs like FPGAs and ASICs – is being spearheaded by teams led by industry bigwigs Xilinx and Intel. The new technologies that come out of this piece will enable ICs with unprecedented bandwidth density, energy efficiency, and reach. The agency also says that researchers from Lockheed Martin, Northrop Grumman, Raytheon, and BAE Systems will be looped into the development of these optical I/O technologies to ensure that the results address the requirements of current and future defense needs. The researchers will also investigate which defense applications could benefit most from this technology.

“The benefits of optical signaling in digital systems have been recognized for a long time,” states PIPES program manager Dr. Gordon Keeler. “The integration of photonics within the package will have enormous benefits for commercial and defense applications, but it comes with considerable challenges. PIPES researchers are working to solve practical technical problems to meet the ambitious goals of the program, which include enabling I/O data rates as fast as 100 terabits/sec at signaling energies below one picojoule per bit [one trillionth of a joule]. At the same time, the teams are studying how to tailor their technologies to address national security applications where operating conditions may be very demanding.”

The second PIPES research area aims to push the optical I/O technologies an order of magnitude beyond even what Xilinx Corporation and Intel seek to accomplish, Keeler says: “To help establish appropriate benchmarks for this research area, we first projected how much data will need to be transported from leading-edge ICs in the 2028 timeframe. Compared to the data capacity of a modern chip today, we may need up to 100 times more off-chip I/O. That’s a petabit [1,000 terabits] per second – roughly the equivalent of the entire world’s internet traffic today – but from a single chip. This is an aggressive benchmark, and we expect the technologies developed in this research area will be less mature at the program’s conclusion, but, if successful, we’ll position photonics to enable disruptive change in future microelectronic systems.”

The research teams selected to explore component technologies and facilitate on-package optical I/O include groups from Sandia National Laboratories, UCSD, UCSB, Columbia University, and University of Pennsylvania. The final research area of the program wants to ask and answer the question of how system architects can both solve the problems and seize the opportunities created by high-performance optical I/O technologies. Researchers from the University of California, Berkeley, are handling this portion.

“If we can seamlessly integrate optical I/O with advanced ICs – and reduce the energy and latency of data movement enough – we eliminate the need to keep data local. It is a major paradigm shift, an opportunity to employ completely different system architectures,” Keeler asserts. “Take optical switching, for example. As data increasingly moves on optical fibers and can be routed long distances, how should we use distributed, disaggregated, and flexible system concepts? This research area will focus on creating novel optical packaging approaches and optical switching technologies to support potential opportunities that emerge through PIPES.”

DARPA ‘s AISS program aims to make on-chip security scalable

According to information from DARPA, the objective of the AISS program is to develop a design tool and IP ecosystem – encompassing tool vendors, chip developers, IP licensers, and the open source community – that will enable security to be inexpensively incorporated into chip designs with minimal effort and expertise, ultimately making scalable on-chip security pervasive.

Serge Leef, a program manager in DARPA’s Microsystems Technology Office (MTO), says of the program: “The security, design, and economic objectives of a chip can vary based on its intended application. As an example, a chip design with extreme security requirements may have to accept certain tradeoffs. Achieving the required security level may cause the chip to become larger, consume more power, or deliver slower performance. Depending on the application, some or all of these tradeoffs may be acceptable, but with today’s manual processes it’s hard to determine where tradeoffs can be made.”

While the threat landscape is ever-evolving, AISS seeks to address four specific attack surfaces that are most relevant to digital ASICs and SoCs: Side-channel attacks, reverse-engineering attacks, supply-chain attacks, and malicious hardware attacks. “Strategies for resisting threats vary widely in cost, complexity, and invasiveness. As such, AISS will help designers assess which defense mechanisms are most appropriate based on the potential attack surface and the likelihood of a compromise,” said Leef.

In addition to incorporating scalable defense mechanisms, AISS seeks to ensure that the IP blocks that make up the chip remain secure throughout the design process and are not compromised as they move through the ecosystem. To further this aim, the program will also aim to inculcate provenance and integrity-validation techniques for preexisting design components by advancing current methods or inventing novel technical approaches, some of which may include IP watermarking and threat detection.

AISS is part of the second phase of DARPA’s Electronics Resurgence Initiative (ERI), a five-year, upwards of $1.5 billion investment in the future of domestic, U.S. government, and defense electronics systems; under Phase II of ERI, DARPA is exploring the development of trusted electronics components, including the advancement of electronics that can enforce security and privacy protections.

ERI Page 3 Investments

In his paper, Moore envisioned building larger circuitry functions out of smaller functional blocks as a means of overcoming limitations to scaling in electronics. With this notion in mind, the ERI “Page 3” Materials & Integration programs seek to answer this question: Can we use the integration of unconventional electronics materials to enhance conventional silicon circuits and continue the progress in performance traditionally associated with scaling? To fully unlock innovation and maintain the DoD’s technical superiority, the Page 3 Design thrust will develop new paradigms for intelligent physical design and reduce the barriers to design of high performance, high-efficiency custom integrated circuits.

MTO’s ERI Page 3 Investments will support research and development in each of these areas: Architectures, Design, and Materials and Integration. To fully unlock microelectronics innovation and maintain DoD’s technical superiority, programs within these Page 3 thrust areas will foster the environment needed for the next wave of U.S. semiconductor advancement.

The “ERI Page 3 Investments” are the next steps in creating an electronics capability that will provide a foundational contribution to U.S. national security. They reflect a collaborative spirit that we hope will lead an electronics industry capable of meeting its own commercial needs and ambitions while simultaneously advancing national defense in the 2025 to 2030 time frame.

Each thrust area will support two separate programs that operate independently of each other. By setting researchers onto the task of investigating vertical, rather than flat or planar integration of microsystem components—as well as new materials, components, and algorithms capable of closing the gap between memory and logic functions—the program managers leading the 3DSoC and FRANC programs hope to create new means of computing vast amounts of information.

Materials & Integration: Can the integration of unconventional materials enhance conventional silicon circuits and continue the progress traditionally associated with scaling?

The Three Dimensional Monolithic System-on-a-Chip (3DSoC) program focuses on developing materials, design tools, and fabrication techniques for building microsystems on a single substrate with a third upward dimension, compared to the usual flat, two-dimensional format for microelectronic chips. A primary payoff of this program could be more efficient packing of logic, memory, and input/output (I/O) elements in ways that dramatically shorten—more than 50-fold—computation times while using less power.

The overall goal of the Domain-specific System on Chip (DSSoC) program is to develop a heterogeneous SoC comprised of many cores that mix general-purpose processors, special-purpose processors, hardware accelerators, memory, and input/output (I/O). DSSoC seeks to enable the rapid development of multi-application systems through a single programmable device.

We did a series of seedling projects at different universities to show that if you can truly mix dense memory and logic in a monolithic 3D stack, for many applications it would be better in absolute terms than a 7-nm processor design sitting next to a memory block. [Monolithic 3D chips have two or more layers of transistors built on the same piece of silicon.] But it’s ultimately very hard because if you’re going to do the monolithic 3D, then your processing needs to be fully compatible, including low-temperature deposition of materials on top of the silicon base.

The overall goal of the Three Dimensional Monolithic System-on-a-Chip (3DSoC) program is to develop 3D monolithic technology that will enable > 50X improvement in SoC digital performance at power. 3DSoC aims to drive research in process, design tools, and new compute architectures for future designs while utilizing U.S. fabrication capabilities.

Foundations Required for Novel Compute (FRANC) program.

The second and related program within this BAA is the Foundations Required for Novel Compute (FRANC) program. Its goal is to transcend the conventional separation of logic and memory functions in what are known as von Neumann architectures (named after the pioneering mathematician, physicist, and computer scientist John von Neumann). The time delay and energy expended in moving data between memory components that store it and processors that act on it are the primary constraints on computer performance today.

Those submitting research proposals for this program will need to show how they might overcome this “memory bottleneck” by developing novel materials, components, and algorithms to speed the movement of memory in and out of logic circuitry or by devising entirely novel structures in which logic and memory circuitry are more intricately meshed than ever before.

The goal of the Foundations Required for Novel Compute (FRANC) program is to define the foundations required for assessing and establishing the proof of principle for beyond von Neumann compute architectures. FRANC will seek to demonstrate prototypes that quantify the benefits of such new computing architectures.

Franc [Framework for Novel Computing], and it looks at new materials for processing-in-memory. We look at where memory is stored and ask: Can those same materials be used for processing information? What you’d like to do is to be able to explore a variety of different materials and use some of their eccentricities to map to the problems that you’re trying to solve. In the past, we’ve been able to show deep neural nets that use nonvolatile memory as part of the computation in both storing weights and doing the summing of, for example, a dot product. That can be more efficient than just using the memory to store information and then having to transfer it all the way back to the processor.

ERI aims to more constructively enmesh the technology needs and capabilities of the defense enterprise with the commercial and manufacturing realities of the electronics industry. To facilitate collaboration between defense and commercial entities, DARPA will publish a regularly updated list of groups interested in teaming on proposals or research. Links to the BAAs and other proposal resources are located in the resources column.

The ERI Page 3 Investments are the next steps in creating a national electronics capability that will provide a foundational contribution to U.S. economic and national security interests. DARPA is eager to work collaboratively with entities that will further the broader cause of the electronics industry while simultaneously advancing national defense.

Software Defined Hardware (SDH) program: Can we enjoy the benefits of specialized circuitry while still relying on general programming constructs through the proper software/hardware co-design?

In architectures, we believe that aggressive specialization is a part of the answer to what happens next. That’s mapping applications to the specific architectural choices. And you already see that in machine learning, where there’s a really hot field in terms of deep neural nets and other implementations. But a lot of our applications are much broader than that. We’re looking to collect the different applications where it makes sense to commit specific specialized resources.

” Software-defined hardware is where the hardware is smart enough to reconfigure itself to be the type of hardware you want, based on an analysis of the data type that you’re working on.” The goal of the Software Defined Hardware (SDH) program is to build runtime-reconfigurable hardware and software that enables near application-specific integrated circuit (ASIC) performance without sacrificing programmability for data-intensive algorithms. SDH will create a hardware/software system that allows data-intensive algorithms to run at near ASIC efficiency without the cost, development time, or single application limitations associated with ASIC development.

The Software Defined Hardware (SDH) program has its sights ultimately on a decision-assistance technology base for designing and manufacturing reconfigurable hardware and software that can run data-intensive algorithms (which are likely to underlie future machine learning and autonomous systems) with the performance of today’s specialty circuits known as Application Specific Integrated Circuits (ASICs).

In that case, the very hard thing is to figure out how to do that data introspection, how to reconfigure the chip on a microsecond or millisecond timescale to be what you need it to be. And more importantly, it has to monitor whether you’re right or not, so that you can iterate and be constantly evolving toward the ideal solution.

Domain-specific System on Chip (DSSoC) program

Today, electronic system performance is limited by the time and power required to access system memory—a restriction often referred to as the “memory bottleneck.” Integrating memory and logic into a single, monolithic 3D SoC stack has the potential to significantly reduce this constraint. The 3DSoC program aims to develop materials, design tools, and fabrication techniques for building microsystems on a single substrate with a third dimension. To achieve the program’s goals, 3DSoC research teams aim to integrate logic, memory, and input/output (I/O) elements in ways that dramatically shorten—more than 50-fold—computation times while using less power.

The Domain-Specific System on a Chip (DDSoC) program of the Architectures thrust is driven by the need to rapidly develop multi-application systems through a single programmable framework. Such a framework would enable SoC designers to mix and match general purpose, special purpose (e.g., ASICs), and hardware accelerator coprocessors, as well as memory and I/O elements, into easily programmed SoCs for applications within specific technology domains. One such domain is software-defined radio, which encompasses mobile communications, satellite communications, personal area networks, all types of radar, and applications in the electronic warfare space.

So what we’re asking is: If you built a new radio from the ground up, what would it need to include to be able to have specialized resources like accelerators and yet also have the ability for a broad community to build on top of it? We’re starting with the software-defined radio domain but then extending that to machine vision and machine learning and other domains to see if you can still have simplified programming models running on top of hyperspecialized hardware. That’s an architecture play, but it’s just as much a software play.

Design: Can we dramatically lower the barriers to modern system-on-chip design and unleash a new era of circuit and system specialization and innovation?

The US Defence Advanced Research Projects Agency (DARPA) has launched a pair of programmes, with $100 million in funding, to further the cause of free and open-source silicon: IDEA and POSH.

Intelligent Design of Electronic Assets (IDEA)

Headed by Andreas Olofsson, formerly of parallel-computing start-up Adapteva and creator of its Parallella development board, the Intelligent Design of Electronic Assets (IDEA) and Posh Open Source Hardware (POSH) programmes are backed by $100 million in funding from a $1.5 billion budget granted to the Electronic Resurgence Initiative (ERI) meta-programme.

Idea is really the intersection of machine learning and electronic design automation (EDA). What we’re trying to do is to be able to capture the capabilities of the designer inside the EDA itself. So that every time you use an EDA package, it gets smarter and your next design is that much easier. Once it works, you can envision a cloud resource where multiple people are sharing and can all get better simultaneously. We’d definitely envision that for the university community. How that breaks down for corporate and proprietary lines is yet to be determined.

The overall goal of the Intelligent Design of Electronic Assets (IDEA) program is to create a “no human in the loop” layout generator that enables users with no electronic design expertise to complete the physical design of electronic hardware within 24 hours. IDEA will develop the algorithms, methodologies, and software required to create an automated, unified layout generator for mixed-signal integrated circuits, systems-in-package, and printed circuit boards.

Northrop Grumman, along with subcontractor JITX, headquartered in Berkeley, California, was one of 11 chosen research teams to perform on the Intelligent Design of Electronic Assets program, one of the efforts part of the ERI. The company will attempt to create an automated electronic circuit layout generator that enables users with no experience to create circuit designs ready for manufacturing within 24 hours. The technology could reduce design times for electronic circuitry from potentially years to a single day.

The first program we did is called Craft. Craft is looking at mechanisms to empower small design teams to do much larger designs. For example, we’ve been working with University of California, Berkeley, on the Chisel design flow. It allows you to write high-level programs to create a system-on-chip. But equally as important to us is to create variants of that chip very quickly. Chisel can port to a new technology node with about 20 percent of the effort of the initial design. That would give us flexibility in manufacturing.

Posh Open Source Hardware (POSH) program

The overall goal of the Posh Open Source Hardware (POSH) program is to create an open source SoC design and verification ecosystem that will enable the cost effective design of ultra-complex SoCs. POSH seeks to create the hardware assurance technology required for signoff-quality validation of open source mixed signal SoCs, develop critical open source IP components, and demonstrate a high-performance open source SoC using the POSH ecosystem.

It’s pretty rare to go to GitHub, find high-quality hardware blocks that are available, and have the verification tools and everything you would need to trust that, even though that block has been altered by many different designers, it is in a state that is useable for your design. Posh is as much about the verification tools as it is about the IP blocks that will be freely available.

The two programmes go hand-in-hand: POSH aims to put together a library of open-source silicon blocks which can be combined to form a system-on-chip (SoC) or other processor, while IDEA will offer a range of tools for automated testing and assembly of said blocks.

‘Most importantly, we have to change the culture of hardware design. Today, we don’t have open sharing,’ Olofsson told the crowd at the Design Automation Conference, a report by attendee EE Times states, ‘but in software, it’s already happened with Linux. Sharing software costs was the best option for the industry, and we can share some hardware components, too.

‘I’ve designed a few boards and found it excruciating,’ Olofsson added. ‘[Board designs quickly] explode into hundreds of details you have to worry about in resistors, capacitors, board size … and there are no optimisation tools, so often, you have a sub-optimal solution. Given the number of boards designed every year, the upside here is enormous.’

The programmes, which are aiming for an interim release in 2020 with final release in 2022, have named commercial partners including Arm, Nvidia, Qualcomm, and Xilinx, along with defence specialist Northrup Grumman, plus 15 universities from across the US.

DARPA’s ERI team expects that new tools that lower the barrier to complex SoC design will enable a new era of innovation in application-specific designs, much in the way that open source software has enabled innovation at the application level.

The programmes’ launch comes amid increasing interest in free and open source silicon projects, in particular the RISC-V architecture which has been picked up by companies including Western Digital, Rambus, and Nvidia for shipment in future products, with Intel – long a proponent of standardising on its own x86 architecture – investing in development of microcontroller products based on the architecture.

DARPA Awards

The Defense Advanced Research Projects Agency has chosen Synopsys to develop a technology to emulate system-on-chips as part of DARPA’s Electronics Resurgence Initiative. Synopsys said it will collaborate with Lockheed Martin and Analog Devices on the Posh Open Source Hardware program that aims to improve the quality of mixed-signal SoC platforms intended for defense and aerospace use. DARPA seeks to establish a foundation of intellectual property building blocks through the POSH project.

The agency noted that ERI will focus on addressing specialized hardware applications that include emulation, artificial intelligence, photonics and security. Synopsys and its partners will use the company’s ZeBu Server emulator in efforts to host a converged platform designed to verify analog and digital IP cores and SoCs.

Arm and DARPA Sign Partnership Agreement to Accelerate Technological Innovation

Arm announced a three-year partnership agreement with the U.S. Defense Advanced Research Projects Agency (DARPA) in August 2020, establishing an access framework to all commercially available Arm® technology. With DARPA’s Electronics Resurgence Initiative gaining momentum, the new agreement will enable the research community that supports DARPA’s programs to quickly and easily take advantage of Arm’s leading IP, tools and support, accelerating innovation in a variety of fields.

“The span of DARPA research activity opens up a huge range of opportunities for future technological innovation,” said Rene Haas, president, IP Products Group, Arm. “Our expanded DARPA partnership will provide them with access to the broadest range of Arm technology to develop compute solutions supported by the world’s largest ecosystem of tools, services and software.”

With more than 170 billion Arm-based chips shipped to date, Arm offers the industry’s most proven IP, providing distributed intelligence from cloud to edge and endpoint. The expanded partnership enables DARPA researchers to have the flexibility and scalability to access vertical market compute from small embedded sensors to high-performance systems.

“DARPA’s programs within the Microsystems Technology Office (MTO) focus on the most advanced challenges in microelectronics; equipping our community with best in class technologies is essential not only for break-through scientific and engineering advances, but also for improved transition into military and commercial applications,” stated Serge Leef, who leads design automation and secure hardware programs in MTO.

To support the work DARPA does, multidimensional collaboration is key. An Arm IP license gives the DARPA community a portal to the world’s largest open compute ecosystem of silicon designers and software developers, enabling the lowest SoC build costs and smallest risk profile. Projects can transition from concepts to real-world deployments in a fast and efficient way, with guidance on everything from hardware verification to physical implementation and software development.

DARPA aims to spur 4th-generation-layered microelectronics manufacturing.

To fortify U.S. microelectronics manufacturing for national security, the agency’s four-year-old Electronic Resurgence Initiative (ERI) is adding two new research areas—developing electronics for extreme environments and manufacturing complex 3D microsystems—as part of its so-called ERI 2.0 effort, reported Carl McCants, special assistant to the DARPA director, ERI, DARPA Microsystems Technology Office.

“[It is] a new era where we are leaving behind this simple device scaling and trying to push into where we are able to get higher performance, dictated by innovations in the third dimension,” McCants explained. “[With integrating heterogeneous components], it is where you’re stacking not one, not two, but three different layers. We went from things being separate to being together on a two-and-a-half-inch interposer, where we had active chips side by side, connected through a passive interposer layer. What we’re now focused on is 3D, where we are stacking things on top of each other, and what you will also see is the fact that we have changed the interconnection pitch [shrinking it 10-100 times]. We have changed the density. This shift from traditional monolithic manufacturing to the 3D changes the form factor.”

ERI 2.0 will continue microelectronics research and development on how to: overcome security threats across the entire hardware life cycle; optimize designing and testing of complex circuits and prototypes; secure communications; realize heterogeneous 3D electronics; harness artificial intelligence hardware to make decisions at the edge faster; and increase information processing density and efficiency.

“DARPA is convinced, moving forward, that 3D manufacturing will further push the boundaries of performance, along with size, weight, power and cost,” McCants said.

The work also includes the creation of a national facility for 3DHI manufacturing through a public-private partnership with industry, academia and government under DARPA’s Next-Generation Microelectronics Manufacturing (NGMM). The effort will enable pre-competition collaboration with the partners in a unique facility.

“By establishing the first domestic, open-access facility for producing next-generation 3DHI prototypes, NGMM will launch a national accelerator in the form of a pilot-line manufacturing facility,” according to a DARPA statement. “Users from across the country can assemble and test their research and development designs without the need for costly investments. Instead, a wider variety of innovators can collaborate under a centralized, holistic approach to advancing, standardizing, and expediting domestic 3DHI prototyping.”