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DARPA DSSoC designing heterogeneous SoC for Military Radar, LIDAR and Software-defined radio (SDR)

The general-purpose computer has remained the dominant computing architecture for the last 50 years, driven largely by the relentless pace of Moore’s Law. As this trajectory shows signs of slowing, however, it has become increasingly more challenging to achieve performance gains from generalized hardware, setting the stage for a resurgence in specialized architectures. Today’s specialized, application-specific integrated circuits (ASICs) — hardware customized for a specific application — offer limited flexibility and are costly to design, fabricate, and program.

 

A system on a chip or system on chip (SoC) is an integrated circuit (also known as a “chip”) that integrates all components of a computer or other electronic system on a single circuit die. Similar to how a microcontroller integrates a microprocessor with peripheral circuits and memory, an SoC can be seen as integrating a microcontroller with even more advanced peripherals like graphics processing unit (GPU), Wi-Fi module, modems or one or more coprocessors– all on a single substrate.   It may also contain digital, analog, mixed-signal, and often radio frequency signal processing functions, depending on the application. SoCs connect to other components too, such as cameras, a display, RAM, flash storage, and much more.

 

Modern computing systems increasingly rely on heterogeneous system-on-chip (SoC) architectures, which combine general-purpose processors with specialized hardware accelerators. This shift toward heterogeneity, however, comes with new challenges, as the required engineering effort scales with increasing heterogeneity

 

Field-Programmable Gate Arrays (FPGAs) and Application-Specific Integrated Circuits (ASICs) can now be used to implement entire SoCs using heterogeneous components such as CPUs, GPUs, accelerators, memories, and specialized IP blocks. SoCs are used across the board in autonomous vehicles, cell phones, software-defined radios, biological monitoring, and a wealth of defense edge applications.

 

Most of these applications share a need to manage large volumes of real-time data from sensors, networked devices, and co-processors and to distribute products and results to displays, storage, and remote destinations. The challenge is to develop the ability to reconfigure or adapt device I/O capabilities flexibly to a range of applications within the target domain to avoid the need to redesign the SoC, and to ease the programming burden associated with routing and managing the dataflow between and across the heterogeneous processing components within the SoC.

 

Domain-specific System on Chip (DSSoC) program

Today, electronic system performance is limited by the time and power required to access system memory—a restriction often referred to as the “memory bottleneck.” Integrating memory and logic into a single, monolithic 3D SoC stack has the potential to significantly reduce this constraint. The 3DSoC program aims to develop materials, design tools, and fabrication techniques for building microsystems on a single substrate with a third dimension. To achieve the program’s goals, 3DSoC research teams aim to integrate logic, memory, and input/output (I/O) elements in ways that dramatically shorten—more than 50-fold—computation times while using less power.

 

The Domain-Specific System on Chip (DSSoC) program seeks to prove that there need not be a continued tradeoff between efficiency, like that found in ASICs, and flexibility, the hallmark of general-purpose processors. The goal of DSSoC is to develop a heterogeneous system-on-chip (SoC) comprised of many cores that mix general purpose processors, special purpose processors, hardware accelerators, memory, and input/output (I/O) devices to significantly improve performance of applications within a domain. DSSoC seeks to enable the rapid development of multi-application systems through a single programmable device.

 

A domain is larger than any one application, where one processor can effectively address problems more efficiently than a general purpose processor but without the challenge, time, and cost of building a special-purpose system like an ASIC. DSSoC is exploring architectures that improve the efficiency of computing through specialized processing while maintaining programmability.

 

The Domain-Specific System on a Chip (DDSoC) program of the Architectures thrust is driven by the need to rapidly develop multi-application systems through a single programmable framework. Such a framework would enable SoC designers to mix and match general purpose, special purpose (e.g., ASICs), and hardware accelerator coprocessors, as well as memory and I/O elements, into easily programmed SoCs for applications within specific technology domains. One such domain is software-defined radio, which encompasses mobile communications, satellite communications, personal area networks, all types of radar, and applications in the electronic warfare space.

 

So what we’re asking is: If you built a new radio from the ground up, what would it need to include to be able to have specialized resources like accelerators and yet also have the ability for a broad community to build on top of it? We’re starting with the software-defined radio domain but then extending that to machine vision and machine learning and other domains to see if you can still have simplified programming models running on top of hyperspecialized hardware. That’s an architecture play, but it’s just as much a software play.

 

To better support the large and growing range of applications needed by the Department of Defense (DoD) to maintain its technological advantage the DSSoC program will seek to produce concepts that provide improved computing efficiency for embedded processing needs while making these systems more programmable. To do this, DSSoC will address critical issues in today’s development cycle that force low-level engineering to port applications onto the specifics of the underlying processors. Specifically, the DSSoC program will seek to develop software stacks that enable better hardware-software co-design by providing vertical integration of tools from the hardware up to the development environment. A second key impact of DSSoC will be the development of intelligent scheduling of applications and data on a heterogeneous processor to make better use of the heterogeneity and parallelism of these systems, whereas today, programming applications for complex systems is a time-consuming, hand-tuned exercise

 

I/O for Heterogeneous SoCs

DARPA’s Domain-Specific System on a Chip (DSSoC) program, for example, improves many aspects of heterogeneous SoC design by analyzing the domain application code, identifying the hardware accelerators best suited for the domain, automating the SoC layout, and managing the compute resources at run-time. However, DSSoC does not address the I/O. This SBIR will address the missing I/O piece and use the information that can be acquired from deep analysis of the application requirements and application code to identify and ideally configure/reconfigure the SoC I/O capabilities needed, and to automate the dataflow into, throughout and out of the SoC.

Given the availability of an approach that incorporates ontology-based deep analysis of the application domain code which informs the design and layout of the target SoC and also supports run-time decision making via a run-time task scheduler, the technical approach may include:

• Analysis of the application code to understand I/O requirements:
o Dataflow into and out of the SoC
o Dataflow between the SoC heterogeneous processing components (CPUs, GPUs, and other accelerators)

• Development of a configuration-driven approach to I/O:
o Demonstrate configurable management of I/O intellectual property (IP), such as double data rate (DDR) support, external interfaces and protocols, high-speed sensor data, etc.
o Implement reconfigurable I/O so that SoC can be repurposed for applications with different I/O requirements
o Development of dynamic automated run-time management of data buffers Support features such as temporary storage, first-in first-out (FIFO) buffers, and double-buffering
o Automatically route data at run time based on application analysis

 

A deep analysis of application domain code can be used to map application compute-intensive functions and kernels to hardware processing elements in a System-on-Chip device (ASIC or FPGA). Development of enhanced, automated, reconfigurable I/O capabilities would open up strong transition opportunities and address feedback from potential transition partners.as well as build on the software/hardware co-design concepts exemplified by the DSSoC program.

 

FPGAs and ASICSs are used extensively in embedded applications across both commercial and DoD/military fields. A commercial example of SoC use is in automobiles for such applications as RADAR and LIDAR processing to support autonomous driving. Military applications include software-defined radio (SDR) communications processing. Ontology-based I/O management for SoCs has the potential to make the development of such embedded and edge applications quicker, easier, and less expensive with shorter time-to-deploy and more flexibility to adapt to changing circumstances.

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