An ARM processor is one of a family of CPUs based on the RISC (reduced instruction set computer) architecture developed by Advanced RISC Machines (ARM). RISC processors are designed to perform a smaller number of types of computer instructions so that they can operate at a higher speed, performing more millions of instructions per second (MIPS). By stripping out unneeded instructions and optimizing pathways, RISC processors provide outstanding performance at a fraction of the power demand of CISC (complex instruction set computing) devices.
ARM processors are extensively used in consumer electronic devices such as smartphones, tablets, multimedia players and other mobile devices, such as wearables. Because of their reduced instruction set, they require fewer transistors, which enables a smaller die size for the integrated circuitry (IC). The ARM processor’s smaller size, reduced complexity and lower power consumption makes them suitable for increasingly miniaturized devices.
The simplified design of ARM processors enables more efficient multi-core processing and easier coding for developers. While they don’t have the same raw compute throughput as the products of x86 market leader Intel, ARM processors sometimes exceed the performance of Intel processors for applications that exist on both architectures.
In March 2017, ARM unveiled its next-generation multi-core micro-architecture designed to boost the performance and efficiency of multi-core Cortex-A processors, which form the basis of many mobile and server SoCs. Known as DynamIQ, the new technology will be heading to automotive, smart home, smartphone, and other connected device markets in the near feature.
The Arm Cortex-A76 CPU is the second generation premium core built on DynamIQ technology. DynamIQ is an evolution of ARM’s existing big.LITTLE technology, the heterogeneous computing architecture that connects together and manages dual ARM CPU core clusters in multi-core configurations. DynamIQ takes this a step further by enabling big.LITTLE configurations of up to eight different CPU cores on a single compute cluster for the first time. This offers SoC designers much greater flexibility than ever before.
Paired with a Cortex-A55 CPU in a scalable DynamIQ big.LITTLE configuration, the Cortex-A76 delivers laptop-class performance with mobile efficiency, bringing the mobile experience (fast responsiveness, always on, always connected) into all classes of intelligent mobile compute devices. With superior energy efficiency and far greater single-threaded performance, the Cortex-A76 CPU extends battery life and improves user experience for sustained high performance across even the most complex compute tasks.
Competition from Open Source RISC-V and MIPS
Arm’s business model is what most in the IP licensing industry now use — an upfront license fee to design with the architecture and then royalties based on the number of chips shipped. Beyond its entry-level zero license fee DesignStart program for Cortex-M0 or Cortex-M3, Arm’s license fees are widely reported to range from $1 million to $10 million.
Product developers no longer have the luxury of two-year product development cycles. And many don’t have the big budgets for licensing fees, often quoted as the huge barrier to entry for system-on-chip (SoC) design. Therefore there has been the rise of open-source architectures such as RISC-V and now MIPS, in the microprocessor industry. Arm’s approach offers limited flexibility compared to a more open architecture. No one wants to spend months negotiating license terms under today’s cost and time-to-market pressures.
One of the promises of open architectures like RISC-V and now MIPS is the ability to ‘play’ on top of the instruction set architectures (ISAs) to innovate and develop your own application-specific SoC. Users can customize them without having to pay an upfront fee. Hence, the cost of entry is lower. It’s not completely free because you still have costs of tools, test, and verification, but there is no license fee for the ISA itself. This is what may hurt Arm in the long term.
RISC-V (pronounced “risk-five”) is a free and open ISA enabling a new era of processor innovation through open standard collaboration. Founded in 2015, the RISC-V Foundation comprises more than 325 members building the first open, collaborative community of software and hardware innovators powering innovation at the edge forward. Born in academia and research, the RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.
The RISC-V Foundation, a non-profit corporation controlled by its members, directs the future development and drives the adoption of the RISC-V ISA. Members of the RISC-V Foundation have access to and participate in the development of the RISC-V ISA specifications and related HW / SW ecosystem. The Foundation has a Board of Directors comprising seven representatives from Bluespec, Inc.; Google; Microsemi; NVIDIA; NXP; University of California, Berkeley; and Western Digital.
In November 2018, the RISC-V Foundation announced a joint collaboration with the Linux Foundation. As part of this collaboration, the Linux Foundation will also provide an influx of resources for the RISC-V ecosystem, such as training programs, infrastructure tools, as well as community outreach, marketing and legal expertise.