We live in an increasingly interconnected world, one in which mobile communications provide a significant element of this interconnectivity. This increasing demand for high speed, low latency networks supporting mobile connectivity is leading the definition of 5th generation mobile networks. These next generation networks are driven not only by changing user demands such as video and cloud applications, but also by the Internet of Things (IoT) and Industrial Internet of Things (IIoT). Both of which introduce machine to machine communication, and in the case of IIOT require reliable networks and low latency response times for critical applications. 5G networks challenge network operators and equipment OEMs as different frequency bands across geographic locations and regulatory environments will present the need to support multiple air interfaces requiring adaptable solutions.
Addressing the challenges presented by 5G requires the capability implement systems which support increased spectral efficiency and ultra-densification. This requires as outlined the ability of the 5G radio to offer a low power, compact, high performance system. This solution also must also scale with the number of antenna to be supported.
To address this Massive Multiple Input Multiple Output (Massive MIMO) architectures are being considered to provide 5G network infrastructure. These consist of multiple antenna systems potentially of up to 1024 antenna. Massive MIMO therefore provides the ability to implement fine grain beam forming, enabling spatial multiplexing. This means that each of the beams can support the full bandwidth, as it is focuses the emitted energy within the beam, it offers increased RF power efficiency. Massive MIMO solutions also enable a message to be broken up and transmitted simultaneously over different paths using multiple antenna.
This change in antenna architecture allows for ultra-densification as antenna tiles can be deployed on buildings, structures and other parts of the surrounding infrastructure moving away from the cell tower. This is especially true if millimetre wavelength communications are used to provide the back-haul capabilities in place of a wired back haul. This change in antenna deployment also brings with it constraints on the radio unit connected to the antenna; constraining not only energy efficiency but also form factor and scalability to scale from small to large scale antenna deployments without radical architectural changes.
It is not just, however, the demands of the 5G infrastructure which present challenges, network operators also bring constraints in the frequency planning. The frequency plan will vary from operator to operator depending upon their licencing and geographic location, but the solution must be configurable to support these use cases.
RFSoC for 5G
Modern electronic systems are based on system on chip (SoC), an integrated circuit (also known as a “chip”) that integrates all components of a computer or other electronic system on a single circuit die. Similar to how a microcontroller integrates a microprocessor with peripheral circuits and memory, an SoC can be seen as integrating a microcontroller with even more advanced peripherals like graphics processing unit (GPU), Wi-Fi module, modems or one or more coprocessors– all on a single substrate.
Central Processing Unit (CPU) is the “brains” of the SoC running most of the code for the Android OS and most of your apps. SoCs use one or more processor cores based on the Arm CPU architecture. An ARM processor is one of a family of CPUs based on the RISC (reduced instruction set computer) architecture developed by Advanced RISC Machines (ARM). It may also contain digital, analog, mixed-signal, and often radio frequency signal processing functions, depending on the application. SoCs connect to other components too, such as cameras, a display, RAM, flash storage, and much more.
As they are integrated on a single electronic substrate, SoCs consume much less power and take up much less area than multi-chip designs with equivalent functionality. Finally, SoCs are much cheaper to design and utilize when compared to multi-chip systems. They are fabricated using a metal-oxide-semiconductor process that is cheaper at volume, and the reduced assembly costs and cabling drives cost down further still. Because of this, SoCs are very common in mobile computing such as tablets, smartphones, smartwatches, netbooks, edge computing markets, and the Internet of Things.
RFSoC integrates RF data converters and FPGA functionality into an SoC specifically targeted at RF applications. Integrating all of these devices enables the shifting of many of the analog signal processing actions – that typically take place close to the antenna in a digital receiver – into the digital domain.
The RFSoC concept address these challenges and more providing a significant reduction in the solution foot print to implement a small radio when compared to a discrete implementation of circa 50%. As the number of antenna supported by the system and signal BW increases so does the number of JESD links required between the SoC and the external convertors. This space saving becomes even more significant thanks to the integration of the RFSoC. This reduction in foot print enables the current proof of concept implementations to become more commercially viable. Implementing a RFSoC approach also brings similar benefits in power reduction when compared to a discrete implementation.
The use of direct sampling and tightly integrated solution which provides both processors and programmable logic also enables flexibility in implementing the final architecture. This is increasingly important in a rapidly evolving domain such as 5G as the final specifications are not yet adopted and approved. This means late revisions to the standard can be accommodated prior to roll out, and future standard revisions can be implemented with greater ease in the field due to the re-programmable nature in the field.
Many of these 5G applications will be in remote and isolated locations as such the security provisions provided by the RFSoC such as anti-tamper features, secure boot and trust zone. Will ensure unauthorised personal cannot access and modify the operation of the radio. Similarly, the RFSoC provides advanced power management options which will allow the device to reduce its power consumption until it is needed. This will be very important in installations applications where 5G service is expected by the user but it is only used occasionally.
RFSoC for military Radars and EW
Successful military operations depend upon the freedom of action in the warfighting domains of air, space, ground, sea, and cyberspace. Today, effective command and control and situational awareness depend upon radio communications and sensors. Domination of the electromagnetic spectrum (EMS) enables joint force commanders to gain tactical, operational, and strategic advantages over a potential adversary. EMS is broken down into frequency bands defined by certain physical characteristics, which include radio waves, microwaves, millimeter waves, infrared, visible light, ultraviolet radiation, x-rays, and gamma rays.
DoD’s growing requirements to gather, analyze, and share information rapidly; to control an increasing number of automated Intelligence, Surveillance, and Reconnaissance (ISR) assets; to command geographically dispersed and mobile forces to gain access into denied areas; and to “train as we fight” requires that DoD maintain sufficient spectrum access,” said DOD’s Electromagnetic Spectrum Strategy unveiled in February 2014.
Today’s radar and electronic warfare systems play a critical role in Domination of the electromagnetic spectrum (EMS): whether detecting enemy aircraft, ships, or land-based vehicles and jamming their communications; guiding missiles; mapping terrain; spoofing enemy radar and so on, dominating the electromagnetic spectrum is paramount success on the battlefield.
As the military threats are becoming more sophisticated we require to develop more efficient, flexible, and adaptable systems while developing more agile and opportunistic spectrum operations to ensure that our forces can complete their missions. In order to address the range of new threats to electromagnetic spectrum dominance, modern radar and electronic warfare systems require increasing numbers of channels and wider bandwidths. Wider bandwidth and more channels mean greater range and trackable targets.
Military Radar and EW systems with multiple channels also suffer from a cost and complexity challenge, in that more channels means more expensive and large RF signal up/down conversion and signal conditioning. A common solution to this is direct RF sampling – a more flexible approach than traditional analog frequency translation and filtering. Direct RF sampling can be implemented in the digital domain, which draws less power and generally costs less.
5G radio units therefore face several challenges in their design to ensure scalability and power efficiency. To support small antenna deployments the core of the radio architecture must be tightly integrated to be able to connect with a small number of antennas at a high data rates. The traditional approach to this challenge would be the combination of a multi giga sample ADCs and DACs with a System on Chip. This approach provides the ability to perform the embedded system design e.g. virtualisation, CloudRAN etc. within the SoC processor cores. While the programmable logic within the SoC is used to implement the ADC/DAC interfaces and signal processing pipeline.
To solve the challenge in case of 5G presented by the network operator licensing and geographical restrictions, the use of direct RF sampling reduces the analog front end components required. These analog front ends are also not programmable or easily adaptable to support licensing or geographic restrictions which requires OEM to use different frequency bands.
Direct sampling is enabled by using ADC and DAC devices with a high sampling frequency and a wide analog input bandwidth, allowing the RF signal to be directly sampled. This removes the need for analog front end, which down convert the signal into the ADC sampling window.
Designing these analog front ends requires specialised skills in the design and careful consideration of the component selection, placement and routing. The designer must also consider component drift with aging and temperature. Direct sampling removes the need for many of these components allowing the processing to be performed within the digital domain.
This means that the RF frond end can handle wider bandwidths than traditional analog technologies while consuming less power. Using very high sample rates in the data converter, as the RFSoC devices do, means that much of the analog filtering and conditioning can be done closer to the antenna, providing a simpler, more flexible front end than has been possible in the past. However, it does come with a trade-off, in that higher sampling discrete ADC and DAC required to directly sample the RF signal have a higher power dissipation.
The RFSoC concept does just that integrating the multi giga sample ADCs and DACs within the same silicon as the SoC, which contains the processing system and programmable logic. This offers a much tighter integrated solution providing the potential for both reduced footprint and power dissipation, while providing a direct sampling RF solution for 5G applications.
Integration of ADC and DAC is not on its own sufficient to address the challenges. To fully address these, the RFSoC must also contain mixers, numerically controlled oscillators, be able to correct gain and phase and support either real or In-phase and Quadrature formatting to realize a fully integrated RFSoC. To further aid system performance, the RFSoC concept also includes optimised processing applications such as Digital Down Conversion and Digital Up Conversion close to the ADC and DAC.
The tightly integrated format of the RFSoC concept enables the device to offer a reduced board area when compared to a similar discrete solution. A typically DAC or ADC may require up to 15mm by 15mm of board space, an application which requires 8 convertors of either type would therefore requires 1800 mm2 of board space. A similar RFSoC solution typically could be packaged in a 30mm by 30mm packaging requiring only 900 mm2 of board space a significant reduction.
Providing this tightly integrated solution not only reduces the required board area but also reduces the overall power dissipation. As power scales with the sampling frequency the power reductions provided by a tightly integrated solution become apparent. Figure three below identifies the power dissipations for a 4 transmit and 4 Receive system at 100 and 200 MHz when implemented in both discrete form, and within a RFSoC. This power saving becomes even more significant if scaled to an 8 transmit and receive solution.
However, it is not just board area and power where we benefit with the RFSoC concept, such a tightly coupled device also offers significant reductions in the complexity of sample clock distribution. This provides a simpler clocking scheme, both at the device-level and also at the system level as the distribution network is less complex, as much is internal to the device. This simpler clocking network reduces the power and cost associated with distributing GHz clocks on the PCB, offering a more efficient overall solution.
The RFSoC concept therefore is capable of providing a more tightly integrated design which offers the potential for a reduced footprint and power dissipation. What remains is to examine the analog / RF performance of the ADC and DAC to ensure the required performance can be provided on the traditionally digital CMOS technology.
Zynq RFSoC family
Applications addressed by the Zynq RFSoC family include remote radio head for massive-MIMO, millimetre wave mobile backhaul, 5G baseband, fixed wireless access, Remote-PHY nodes for cable, radar, test and measurement, SATCOM, and Milcom/Airborne Radio and other high performance RF applications.
Zynq UltraScale+ RFSoC devices now make viable the most bandwidth intensive systems for next generation wireless infrastructure. 5G imperatives – ranging from 5X bandwidth, 100X user data rates, and 1,000X greater network capacity – would be unattainable without breakthroughs at the system level. The integration of discrete RF data converters and signal chain optimisation in Zynq UltraScale+ RFSoCs allow remote radio head for Massive-MIMO, wireless backhaul, and fixed wireless access to realise high channel density with 50-75% power and footprint reduction. Multiple integrated SD-FEC cores enable 10-20X system throughput vs. a soft core implementation for 5G baseband within stringent power and thermal constraints.
Zynq RFSoCs also deliver the needed performance and adaptability for key government programmes such as the Multi-function Phased Array Radar (MPAR) initiative to combine the functions of several national radar networks into a single system for aircraft and weather surveillance. Because these leading-edge systems must operate in real-time, the inherent integration of RF-Analogue makes the Zynq UltraScale+ RFSoC a suitable solution. Zynq RFSoC devices are currently designed into the Rockwell Collins’ Common Module beamformer for the DARPA Arrays at Commercial Time Scales (ACT) program, which aims to shorten design cycles and in-field updates while pushing past traditional barriers for delivering radar arrays.
As these trends for wider bandwidth and more channels proliferate, the need for a flexible hardware platform becomes greater and greater. FPGA-based digital receivers – the front end of a radar or EW system – that leverage FMC modules for analog-to-digital conversion systems have provided a flexible, high-performance solution to current challenges. The flexibility of the system derives from the ability to upgrade hardware pieces – like the FMC module – when the performance requirement changes, or when the next generation of technology
is introduced. While flexibility at the hardware level can help overcome the stringent requirements for wider bandwidth, more
channels and high adaptability, even greater flexibility could be provided if this flexibility could be pushed closer to the antenna.
The Zynq UltraScale+ RFSoC devices – a new innovation from Xilinx – provide such a solution. This family of devices features an integrated ADC (up to 16 12-bit channels sampling at 4.0 GSPS), DAC (up to 16 14-bit channels sampling at 6.4GSPS), configurable logic elements, multi-processor embedded ARM Cortex-A53 application processing unit (APU), and an ARM real time processing unit (RPU). Integrating all of these devices enables the shifting of many of the analog signal processing actions – that typically take place close to the antenna in a digital receiver – into the digital domain.
Doing so helps reduce the RF signal processing chain complexity, standardize on one set of flexible hardware to address a variety of applications, maximize input/output channel density without sacrificing wide bandwidth and leverage heterogeneous processing capabilities – all of this while taking advantage of the Zynq architecture’s built-in security features that help keep IP safe.
References and Resources also include: