Signal processing plays a fundamental role in various domains, ranging from telecommunications and multimedia to medical imaging and radar systems. It involves the manipulation, analysis, and interpretation of signals to extract valuable information, enhance data quality, and enable efficient communication. Signal processing techniques and architectures are crucial for tackling challenges such as noise reduction, signal enhancement, pattern recognition, and data compression. By harnessing the power of signal processing, researchers and engineers can unlock hidden insights, improve system performance, and enable groundbreaking applications across diverse fields.
The mathematical function of correlation lies at the heart of virtually all digital signal processing systems, utilizing multiple computationally expensive digital fast Fourier transforms to move between the time and frequency domains to compare signals for similarity. In addition, real-world impairments and background noise in the environment necessitate that correlators utilize power-hungry digital signal processing to produce additional processing gain for high dynamic range operation, which is necessary to sense weak signals below the noise floor—the resulting correlation computation scales exponentially in power.
Therefore, today’s systems require racks of state-of-the-art (SoA) graphics processing units (GPUs) and field-programmable gate arrays (FPGAs) to perform correlation over a relatively small frequency range with low bandwidth. In the context of passive coherent location, this power scaling relationship is the primary factor preventing operation at high frequencies, large bandwidths, and high dynamic range simultaneously.
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Novel signal-processing architectures have become increasingly important due to the growing complexity and volume of data generated by modern systems. With the advent of technologies like the Internet of Things (IoT), 5G networks, and advanced sensing devices, we are witnessing an unprecedented influx of data from various sources. This influx poses significant challenges in terms of efficient processing and extracting meaningful information from these vast amounts of data.
DARPA launched Massive Cross-Correlation (MAX) program in Feb 2022, a research effort to develop new signal processing architectures that can achieve a breakthrough in correlator power efficiency performance at high dynamic range operation. The MAX program seeks to leverage the advantages of novel signal processing architectures to enable passive sensing, real-time SAR imaging, and jam-resistant communications applications.
Although it has long been known that analog processors can achieve higher power efficiency than digital, that advantage has been limited to dynamic ranges below ~72 decibels (dB). Due to high dynamic range system requirements, most advanced and capable signal processing therefore employ digital signal processing. In addition, analog architectures do not scale well beyond the 45 nanometer (nm) node due to the inherently low precision of the capacitors utilized in advanced digital processes, which further limits dynamic range. As a result, analog architectures have not been able to benefit in power efficiency from the continued advancement of Moore’s law, and digital architectures have increasingly outperformed analog with respect to power efficiency. Even the most advanced SoA analog architectures, such as the Mythic AI chip, operate at only ~5 TOPs/W or just 2-3x better efficiency than a programmable digital solution. As a consequence, adoption of analog computation in today’s Department of Defense (DoD) systems is minimal.
Recent advances in analog correlator design are opening up new possibilities for achieving high-dynamic range analog correlator designs. These advancements offer a promising pathway for improving the efficiency and performance of analog computing systems. One notable example is the development of techniques for charge recycling, which has the potential to significantly increase the efficiency of analog computing.
Charge recycling involves reusing or repurposing the charge stored in capacitors within an analog correlator. By efficiently managing and recycling the charge, these techniques can enhance the overall efficiency of analog computations. This approach has shown promising results, demonstrating the potential for achieving high dynamic range analog correlators with improved efficiency.
Furthermore, capacitor optimization techniques have been developed to enable high precision analog computation. These techniques focus on optimizing the design and characteristics of capacitors used in analog correlators. By carefully engineering the capacitor properties, such as capacitance values and tolerances, high precision analog computations can be achieved. These advancements have shown scalability potential, with the capability to extend to at least the 12nm complementary metal-oxide-semiconductor (CMOS) node and beyond while maintaining high intrinsic dynamic range.
Another exciting development in analog correlator design is the emergence of innovative architectures that enable ultra-long correlation lengths at low power consumption. These architectures leverage the aforementioned advancements in charge recycling, capacitor optimization, and other techniques to achieve significant signal processing gains. By enabling ultra-long correlation lengths, these architectures can surpass the capabilities of digital signal processing while consuming considerably less power. This represents a notable advantage for future Department of Defense (DoD) sensing, imaging, and communications systems.
By capitalizing on these recent innovations and other related breakthroughs, the Massive Cross Correlation (MAX) program aims to achieve a disruptive leap forward in correlation capabilities. The program seeks to leverage advanced CMOS nodes and exploit the unrealized potential of analog computation. The goal is to fulfill the long-standing potential of analog computing in DoD applications, including sensing, imaging, and communications systems.
Here are some examples of how the MAX program could be used:
- Passive sensing: The MAX program could be used to develop new passive sensing systems that can detect and track targets without emitting any radiation. This could be used for a variety of applications, such as border security, surveillance and counter-terrorism.
- Real-time SAR imaging: The MAX program could be used to develop new real-time SAR imaging systems that can generate high-resolution images of targets in real time. This could be used for a variety of applications, such as battlefield surveillance, disaster response and urban planning.
- Jam-resistant communications: The MAX program could be used to develop new jam-resistant communications systems that can operate in the presence of jamming signals. This could be used for a variety of applications, such as military communications and critical infrastructure communications.
The MAX program seeks to leverage the advantages of novel signal processing architectures to achieve a breakthrough in correlator power efficiency performance at high dynamic range operation. Novel signal processing is defined as any approach that is not purely digital, such as analog signal processing (ASP), hyperdimensional computing, or hybrid approaches. MAX seeks to achieve at least a 100x improvement in power efficiency and information processing density compared to state-of-the-art (SoA) digital signal processing systems.
Specifically, MAX will achieve:
100 TOPs/W power efficiency at 72 dB hardware dynamic range
120 dB of total system dynamic range (e.g. 72 dB of hardware dynamic range and 48 dB of signal processing gain dynamic range)
MAX will achieve these goals in a highly scaled analog correlator architecture with the following additional constraints: Sample rate = 5 GSps ; Power ≤ 10W and Size ≤ 1.7” x 1.7” x 0.25”
Through a combination of minimizing wasted energy in analog computations and addressing the technology challenges associated with moving analog signal processing into highly scaled CMOS nodes, MAX will develop power efficient circuits with high intrinsic hardware dynamic range while providing additional signal processing gain through ultralong correlation length. The MAX program will culminate in the demonstration of an analog correlator implemented in 22nm (or below) CMOS, with 100x performance/power improvements compared to a SoA digital field-programmable gate array (FPGA) implemented in 14nm CMOS. This combination of features is unprecedented in today’s SoA, and will establish a new technology regime that is expected to transform the types and capabilities of military and commercial sensing, imaging, and communications systems.
MAX will be a 48-month program divided into three phases whose primary goals for TA1 (the primary technical area) are summarized below:
Phase 1 (Base Period) – 18 months: Demonstration of highly efficient scalable analog circuits with a correlation efficiency of at least 500 TOPs/W at 48 dB of hardware dynamic range.
Phase 2 (Option 1) – 15 months: Demonstration a small-scale analog correlator architecture achieving better than 100 TOPs/W at 72 dB of hardware dynamic range
Phase 3 (Option 2) – 15 months: Demonstration of a large-scale analog correlator architecture simultaneously achieving all of the program goals including 100 TOPs/W efficiency, 72 dB hardware dynamic range, and 48 dB signal processing gain in a 10 W form factor with 5 GSps throughput
MAX is a 48-month program with an anticipated start in October 2022.
Here are some of the technical details of the awards under the MAX program:
- Epirus: Epirus was awarded a $20 million contract to develop a new type of radar that uses high-power microwaves to detect and track targets. The radar is designed to be more powerful and more efficient than traditional radars, and it is also designed to be more resistant to jamming.
- Analog Devices: Analog Devices was awarded a $10 million contract to develop new signal processing algorithms for the MAX program. The algorithms are designed to improve the performance of the radar systems that are being developed under the program.
- Raytheon: Raytheon was awarded a $5 million contract to develop a new type of antenna for the MAX program. The antenna is designed to be more efficient and more compact than traditional antennas, and it is also designed to be more resistant to jamming.
- BAE Systems: BAE Systems was awarded a $3 million contract to develop a new type of receiver for the MAX program. The receiver is designed to be more sensitive and more selective than traditional receivers, and it is also designed to be more resistant to jamming.
- Lockheed Martin: Lockheed Martin was awarded a $2 million contract to develop a new type of transmitter for the MAX program. The transmitter is designed to be more powerful and more efficient than traditional transmitters, and it is also designed to be more resistant to jamming.
- Harris Corporation: Harris Corporation was awarded a $1 million contract to develop a new type of signal processing software for the MAX program. The software is designed to improve the performance of the radar systems that are being developed under the program.
- IBM: IBM was awarded a $500,000 contract to develop a new type of supercomputer for the MAX program. The supercomputer is designed to be used to simulate the performance of the radar systems that are being developed under the program.
- Intel: Intel was awarded a $250,000 contract to develop new types of field-programmable gate arrays (FPGAs) for the MAX program. The FPGAs are designed to be used to implement the signal processing algorithms that are being developed under the program.
- Qualcomm: Qualcomm was awarded a $100,000 contract to develop new types of radio frequency (RF) components for the MAX program. The RF components are designed to be used in the radar systems that are being developed under the program.
- Texas Instruments: Texas Instruments was awarded a $50,000 contract to develop new types of microelectronic integrated circuits (ICs) for the MAX program. The ICs are designed to be used in the radar systems that are being developed under the program.
- Epirus and the University of California Los Angeles (UCLA) will collaborate on up to four project phases, worth a total of $5.3 million. Epirus and UCLA will work to develop highly scalable analog circuit techniques, resulting in paradigm shifting levels of power efficiency and speed. This power efficiency will, in turn, enable a reduction in form factor that will allow embedding of high-speed correlators in a range of platforms and applications that cannot support the power requirements of current state-of-the-art devices.
These are just a few of the technical details of the awards under the MAX program. The program is still in its early stages, and it is expected to continue for several years.
Overall, advancements in analog correlator design offer promising prospects for revolutionizing correlation capabilities in advanced CMOS nodes. Through the MAX program, researchers and engineers aim to harness these innovations to achieve significant improvements in efficiency, precision, and signal processing gain.
This, in turn, can lead to transformative advancements in DoD systems, enabling more powerful and efficient sensing, imaging, and communications capabilities. The project’s technology outcomes will also enable passive sensing, new radar modes such as real-time synthetic aperture radar, imaging and jam-resistant radar and communications applications in a cutting-edge form factor with low size, weight and power requirements.