Modern warfare is increasingly dependent on microelectronics capabilities that sense the environment, convert the signals into data streams, process the information, and generate a response. In this sense, Aerospace and Defense (A-D) systems are quite similar to commercial systems that perform communications and computations, while taking advantage of the advancement of semiconductor density, functionality, and cost reduction due to Moore’s Law. There is the everincreased demand for more data throughput through wired and wireless systems. Cellular systems have migrated from 3G to 4G and now 5G architectures which improves bandwidth ~10X with each generation. DoD systems for communications, radar, and sensing generally require wider bandwidths, higher dynamic range, and higher transmit power, as well as specialized frequency bands and security requirements that the commercial side does not require.
Several characteristics of the A-D sector create unique challenges, They are high performance so require access to leading silicon nodes and advanced packaging technologies to maintain advantage in specific technical metrics (e.g., digitization over wide bandwidths and at high dynamic range. They require High Reliability as they need to survive in harsh environments, prioritize human safety in high-risk environment. They require Long Product Lifecycles therefore managing parts obsolescence and upgradability is important. Compared to commercial sector they are Low Volumes hence require access to supply chain that provides high product mix, and business models where
NRE is managed without high volumes for amortization. finally Security is paramount and hence require secure domestic supply chain and/or verification technologies.
Heterogeneous integration is a factor in all of these challenges, whether by adding new twists to the challenges with multiple device technologies or by solving some of them with modular designs and assemblies. Most specifically, heterogeneous integration directly addresses the high-performance challenge for the A-D sector.
Heterogeneous integration via 2.5D technology is approaching mainstream status, with industry leaders such as Xilinx, Intel, Nvidia, and AMD using it in their leading products. They have identified the benefits of splitting up silicon functionality, whether to improve yield with smaller chips, as Xilinx did with their pioneering FPGA “slices,” or to enable the integration of different types of devices.
Monolithic System on a Chip solutions are becoming increasingly limited for A-D applications. Sustaining Moore’s Law by increasing the core count on a die is not feasible as memory access bottlenecks prevail and die size and complexity become prohibitively expensive. Diversity in process nodes and materials are needed (CPUs, GPUs, FPGAs) for enhancing performance, energy efficiency and programmability. Similarly, RF/mm-wave devices and data converters are needed for communications and sensing. Heterogeneous integration offers a way to address these limitations and sustain Moore’s Law through interconnect length reductions and optimal combinations of different device technologies. The A-D sector must adapt and adopt innovation and market drivers from the commercial semiconductor industry.
DARPA has led the way in advancing Heterogeneous Integration Technology through a number of programs. The DARPA DAHI program demonstrated the feasibility of 2.5D HI for integration of CMOS devices with high-performance III-V devices through both die-to-wafer and wafer-to-wafer bonding techniques. The DARPA CHIPS program (which is still on-going) is developing a 2.5D chiplet ecosystem and a set of standard interfaces for chiplet to chiplet communications.
By enabling this heterogeneous integration capability, DAHI seeks to establish a new paradigm for microsystems designers to utilize a diverse array of materials and device technologies on a common silicon-based platform. DARPA launched Common Heterogeneous Integration and Intellectual Property (IP) Reuse Strategies (CHIPS) program seeking innovative insights on how standard interfaces and IP reuse can be to create custom circuits in a fraction of today’s time and cost, with conventional methods for both digital and analog systems.
On June 1, 2017, the DARPA Microsystems Technology Office (MTO) announced a new Electronics Resurgence Initiative (ERI) to ensure far-reaching improvements in electronics performance well beyond the limits of traditional scaling. The ERI will draw on new and existing DARPA programs to make a significant investment into enabling circuit specialization and managing complexity. The foundation for the Initiative has been building for a number of years in the form of existing MTO programs such as DAHI, CHIPS and CRAFT, which address ERI’s three research pillars: materials and integration, circuit design, and systems architecture.
These DARPA Programs are in line with US’s third offset strategy, which according to Hagel is “This new initiative is an ambitious department-wide effort to identify and invest in innovative ways to sustain and advance America’s military dominance for the 21st century.” Instead of such custom-tailored, tightly integrated systems, you want a modular and open architecture where you can easily replace a component — hardware or software — without disrupting the rest of the system. Instead of a relatively small number of pricey manned platforms, you want a “heterogeneous” mix of manned and unmanned vehicles of all kinds, from 130-foot robotic ships to disposable handheld drones. Instead of architectures designed for a specific kind and size of force, you want systems that can scale up and down as the force changes.
DARPA’s Diverse Accessible Heterogeneous Integration (DAHI)
Complex Defense systems, such as RADAR, communications, imaging and sensing systems rely on a wide variety of microsystems devices and materials. These diverse devices and materials typically require different substrates and different processing technologies, preventing the integration of these devices into single fabrication process flows. Thus, integration of these device technologies has historically occurred only at the chip-to-chip level, which introduces significant bandwidth and latency-related performance limitations on these systems, as well as increased size, weight, power, and packaging/assembly costs as compared to microsystems fully integrated on a single chip.
The development of compound semiconductor (CS) electronics has been motivated by their many superior materials properties relative to silicon. For example, high electron mobility and peak velocity of InP-based material systems have resulted in transistors with fmax above 1THz as well as ultra-high-speed mixed-signal circuits. The wide energy bandgap of GaN has enabled large voltage swings as well as high breakdown voltage RF power devices. Excellent thermal conductivity of SiC also makes tens of kilowatt-level power switches possible. Meanwhile, in the photonics domain, III-V materials based on InP and GaAs have been a key enabler due to the excellent photonic properties associated with the direct band gap of these materials. The indirect band gap of silicon makes optical gain in this material very inefficient, greatly limiting its utility in both discrete and integrated photonic systems. On the other hand, silicon CMOS-based technologies have achieved tremendous levels of complexity and integration, while also demonstrating high levels of yield and manufacturability.
The DAHI program is developing transistor-scale heterogeneous integration processes to intimately combine advanced compound semiconductor (CS) devices, as well as other emerging materials and devices, with high-density silicon complementary metal-oxide-semiconductor (CMOS) technology.
This technology is currently enabling RF/mixed signal circuits with revolutionary performance. For example, InP HBT + CMOS technology is being utilized in advanced DACs and ADCs with CMOS-enabled calibration and self-healing techniques for correcting static and dynamic errors in situ. Such CMOS-enabled self-healing techniques are expected to more generally enable improved CS-based circuit performance and yield in the presence of process and environmental variability, as well as aging. DAHI is also expected to enable the integration of high power CS devices with silicon-based linearization techniques to realize highly power efficient transmitters.
The ultimate goal of DAHI is to establish a manufacturable, accessible foundry technology for the monolithic heterogeneous co-integration of diverse devices and complex silicon-enabled architectures on a common substrate platform. Such integration would increase the capabilities of high-performance microsystems for the U.S. Military. The DAHI program will address the following key technical challenges (1) heterogeneous integration process development, (2) high-yield manufacturing and foundry establishment, and (3) circuit design and architecture innovation.
Microsystem devices and materials that may be integrated include:
- Silicon complementary metal-oxide-semiconductor (Si CMOS) for highly integrated analog and digital circuits
- Gallium Nitride (GaN) for high-power/high-voltage swing and low-noise amplifiers
- Gallium Arsenide (GaAs) and Indium Phosphide (InP) heterojunction bipolar transistors (HBT) and high-electron mobility transistors (HEMT) for high speed/high-dynamic-range/low-noise circuits
- Antimonide-based compound semiconductors for high-speed, low-power electronics
- Compound semiconductor optoelectronic devices for direct-bandgap photonic sources and detectors, as well as or silicon-based structures for modulators, waveguides, etc.
- Microelectromechanical (MEMS) components for sensors, actuators and RF resonators
- Thermal management structures
DARPA’s efforts in heterogeneous integration began with the Compound Semiconductor Materials on Silicon (COSMOS) program. COSMOS is now a DAHI program thrust, along with Electronic-Photonic Heterogeneous Integration (E-PHI) and DAHI Foundry Technology thrusts.
The program demonstrated capabilities that would not have been possible in monolithic implementations, while uncovering several challenges in design, fabrication, and assembly along the way. The DAHI program has served as the baseline for heterogeneous integration at DARPA and beyond in the DoD.
DARPA’s “CHIPS,” or Common Heterogeneous Integration and Intellectual Property (IP) Reuse Strategies Program
Today’s leading edge electronic designs are complex, expensive, and often involve teams spread across the globe; factors that have driven drastic growth in non-recurring engineering (NRE) costs. Additionally, the monolithic nature of these designs means that any change to a portion of the chip requires a re-spin of the entire chip. The high cost notwithstanding, these application specific integrated circuits (ASICs) are unrivaled in their performance. Many large commercial designers can spread these costs over the large volumes of consumer products, but for low-volume customers like the DoD, start-up companies, and academia, these mounting costs have restricted access to the latest device technologies (or “nodes”). Overseen by Linton Salmon, a program manager in DARPA’s Microsystems Technology Office (MTO), the CRAFT program seeks to develop new fast-track circuit-design methods, multiple sources for integrated circuit fabrication, and a technology repository that will facilitate reuse of proven solutions.
DARPA launched “CHIPS,” or Common Heterogeneous Integration and Intellectual Property (IP) Reuse Strategies Program with aim to devise a physical library of component chips, or chiplets, that can be assembled in a modular fashion. A chiplet is a functional, verified, modular re-useable physical IP block. They can be processors, converters,
memory, waveform generators, accelerators, filters, etc.
Another problem DARPA’s trying to solve is the cost and complexity of intellectual property (IP). Using a standard circuit board often requires the manufacturer to buy multiple patent licenses for unneeded functions. The US Department of Defense thinks that if chiplets are separated by function, it would reduce costs by limiting the required IP. “This should be a win for both the commercial and defense sectors,” DARPA’s Dr. Daniel Green asserts.
The library of custom and commercial “chiplets” shall individually embody a particular function, such as data storage, computation, signal processing, and managing the form and flow of data. By assembling and integrating dozens of chiplets, mosaic style, on a so-called interposer, which is like a printed circuit board writ small, all of those microsystems’ functions could be performed in a much closer huddle and can perform more efficiently than if they were distributed in the usual way among a suite of chips attached to a conventional PCB.
“We are trying to push the massive amount of integration you typically get on a printed circuit board(PCB) down into an even more compact format,” Dr. Daniel Green, manager of the new program said. DARPA held the kickoff meeting for its new CHIPS program where a dozen prime contractors have been named, among them Intel, Micron, and Cadence Design Systems. The other designated contractors include Lockheed Martin, Northrop Grumman, and Boeing, Synopsys, Intrinsix Corp., and Jariet Technologies, University of Michigan, Georgia Institute of Technology, and North Carolina State University. Central to the design and intention of the program, says DARPA, is the creation of a new community of researchers and technologists that mix-and-match mindsets, skillsets, technological strengths, and business interests. The prime contractors are expected to help build this community by working with others.
A primary driver of CHIPS is to develop a novel, industry-friendly architectural strategy for designing and building new generations of microsystems in which the time and energy it takes to move signals—that is, data—between chips is reduced by factors of tens or even hundreds. “This is increasingly important for the data-intensive processing that we have to do as the data sets we are dealing with get bigger and bigger,” Green said. The new architectural strategy at the program’s heart could open new routes to computational efficiencies required for such feats as identifying objects and actions in real-time video feeds, real-time language translation, and coordinating motion on-the-fly among swarms of fast-moving unmanned aerial vehicles (UAVs).
One technique for addressing rising cost and complexity has been the use of a modular design flow that subdivides a system into functional circuit blocks, called IP blocks. IP block refers to intellectual property captured in a pre-designed functional circuit block. Examples of IP blocks include, but are not limited to, timing circuits, filters, waveform generators, embedded processors, data converters, amplifiers, fast Fourier transforms (FFTs), serializer-deserializers (SERDES), and memory.
“Key to the success of CHIPS will be standards and interfaces, and this means we will be working with a community, not all by ourselves,” said Green. The CHIPS team expects to use input from the RFI and a workshop anticipated to occur later this summer to prepare a Broad Agency Announcement (BAA). The BAA, which will also be posted on fbo.gov, will specify the program’s technical goals and how potential performers can submit proposals.
A major achievement in the program was the adoption of Intel’s Advanced Interface Bus (AIB) as the low-power die-to-die electrical interface. AIB offers a 1-Gbps per lane SDR transfer rate for control signals and a 2-Gbps DDR transfer rate for data.
Chips is part of a larger DARPA effort, the Electronics Resurgence Initiative, which aims to build an electronics community that mixes the best of the commercial and defense capabilities for national defense. The ERI will involve an expenditure of at least $200 million annually over the next four years.
Arm and TSMC Demonstrate Industry’s First 7nm Arm-based CoWoS Chiplets for High-Performance Computing
Arm and TSMC, the High-Performance Computing (HPC) industry leaders, today announced in Sep 2019 an industry-first 7nm silicon-proven chiplet system based on multiple Arm® cores and leveraging TSMC’s Chip-on-Wafer-on-Substrate (CoWoS®) advanced packaging solution. This single proof-of-concept chiplet system successfully demonstrates the key technologies for building an HPC System-On-Chip (SoC) with Arm-based cores operating at 4GHz in a 7nm FinFET process. The chiplet system also demonstrates for SoC designers an on-die, bi-directional interconnect mesh bus operating at 4GHz, and a chiplet design methodology connected by an 8Gb/s inter-chiplet interconnect over a TSMC CoWoS interposer.
Rather than the traditional SoC approach of combining every system component onto a single die, chiplet designs are optimized for modern HPC processors which partition large multi-core designs into smaller chipsets. This efficient approach enables functions to be split into smaller, separate dies which provide for the flexibility of producing each chiplet on different process technologies, as well as delivering better yields and overall cost effectiveness. And to ensure the highest levels of performance, chiplets must communicate with each other through dense, high-speed, high-bandwidth connections. To address this challenge, this chiplet system features a unique Low-voltage-IN-Package-INterCONnect (LIPINCONTM) developed by TSMC which has reached data rates of 8Gb/s per pin with excellent power efficiency results.
The chiplet system is comprised of a dual-chiplet CoWoS implemented in 7nm, with each chiplet containing four Arm Cortex®-A72 processors and an on-die interconnect mesh bus. The die-to-die inter-chiplet connection features scalable 0.56pJ/bit (pico-Joules per bit) power efficiency, 1.6Tb/s/mm2 (terabits per second per square millimeter) bandwidth density, and 0.3V LIPINCON low-voltage interface achieving 8GT/s (Giga Transactions per second) and 320GB/s bandwidth. The chiplet system was taped out in December 2018, and produced in April 2019.
“This demonstration chip is an excellent showcase of the system integration capabilities we offer to our customers,” said Dr. Cliff Hou, Vice President of Technology Development for TSMC. “TSMC’s CoWoS advanced packaging technology and LIPINCON inter-chiplet interface enable customers to partition large multi-core designs into smaller chiplets that deliver better yield and better economics. This Arm and TSMC collaboration further unleashes our customers’ innovations in high-performance SoC design for cloud-to-edge infrastructure applications.”