Parallelism – or the act of several processors simultaneously executing on an application or computation – has been increasingly embraced by the microelectronics industry as a way of sustaining demand for increased system performance. Today, parallel computing architectures have become pervasive across all application domains and system scales – from multicore processing units in consumer devices to high-performance computing in DoD systems.
However, the performance gains from parallelism are increasingly constrained not by the computational limits of individual nodes, but rather by the movement of data between them. When residing on modern multi-chip modules (MCMs), these nodes rely on electrical links for short-reach connectivity, but once systems scale to the circuit board level and beyond, the performance of electrical links rapidly degrades, requiring large amounts of energy to move data between integrated circuits. Expanding the use of optical rather than electrical components for data transfer could help significantly reduce energy consumption while increasing data capacity, enabling the advancement of massive parallelism.
Silicon photonics offers a potential breakthrough in optical interconnections that provide bandwidth and power performance, to remove communication bottlenecks within integrated circuit chips that incorporate over a billion transistors, and between integrated circuits in single boards that provide multi-teraflop (1012) computing capacity.
That trend is optical interconnection of components, now moving from systems to boards to chip packages to chips themselves, says Lionel Kimerling, the Thomas Lord Professor in Materials Science and Engineering and director of the MIT Microphotonics Center. “There are significant challenges for each one of those steps. Cost, bandwidth density, and power efficiency are the big three, and cost is the one that’s really controlling the entry of photonics into the system.
Signaling over optical fibers enables the internet today and optical transceivers are ubiquitous in data centers, yet digital systems still rely upon the movement of electrons over metal wires to push data between integrated circuits (ICs) on a board. Increasingly, the limitations of electrical signaling from the chip package restrict overall bandwidth and signaling efficiency, throttling the performance of advanced systems.
DARPA launched PIPES program in 2019, to explore ways to expand the use of optical components to address these constraints and enable digital microelectronics with new levels of performance. PIPES seeks to enable disruptive system scalability by developing optical signaling technologies for digital microelectronics. The program will employ intimate integration of photonics with advanced integrated circuits to yield unprecedented system connectivity.
“Today, microelectronic systems are severely constrained by the high cost of data movement, whether measured in terms of energy, footprint, or latency,” said Dr. Gordon Keeler, program manager in DARPA’s Microsystems Technology Office (MTO). “Efficient photonic signaling offers a path to disruptive system scalability because it eliminates the need to keep data local, and it promises to impact data-intensive applications, including machine learning, large scale emulation, and advanced sensors.”
Photonic transceiver modules already enable optical signaling over long distances with high bandwidth and minimal loss using optical fiber. Bottlenecks result, however, when data moves between optical transceivers and advanced integrated circuits in the electrical domain, which significantly limits performance. Integrating photonic solutions into the microelectronics package would remove this limitation and enable new levels of parallel computing.
Photonics in the Package for Extreme Scalability (PIPES) program
A new DARPA program, the Photonics in the Package for Extreme Scalability (PIPES) program, seeks to enable future system scalability by developing high-bandwidth optical signaling technologies for digital microelectronics. Working across three technical areas, PIPES aims to develop and embed integrated optical transceiver capabilities into cutting-edge MCMs and create advanced optical packaging and switching technologies to address the data movement demands of highly parallel systems. The efficient, high-bandwidth, package-level photonic signaling developed through PIPES will be important to a number of emerging applications for both the commercial and defense sectors.
PIPES will develop optical I/O for emerging data movement needs of commercial and military systems. PIPES seeks to emplace integrated optical transceiver capabilities into cutting-edge multi-chip modules (e.g., field-programmable gate arrays (FPGAs), graphical processing units (GPUs), central processing units (CPUs), and application-specific integrated circuits (ASICs)) for 2023-era microelectronics with performance well beyond currently available solutions.
The first technical area of the PIPES program is focused on the development of high-performance optical input/output (I/O) technologies packaged with advanced integrated circuits (ICs), including field programmable gate arrays (FPGAs), graphics processing units (GPUs), and application-specific integrated circuits (ASICs). Beyond technology development, the program seeks to facilitate a domestic ecosystem to support wider deployment of resulting technologies and broaden their impact.
In parallel, PIPES aims to develop novel optical I/O approaches and advanced optical packaging and switching technologies to satisfy data movement demands of highly parallel systems in the 2028 timeframe.
Projections of historic scaling trends predict the need for enormous improvements in bandwidth density and energy consumption to accommodate future microelectronics I/O. To help address this challenge, the second technical area will investigate novel component technologies and advanced link concepts for disruptive approaches to highly scalable, in-package optical I/O for unprecedented throughput.
The successful development of package-level photonic I/O from PIPES’ first two technical areas will create new challenges for systems architects. The development of massively interconnected networks with distributed parallelism will create hundreds to thousands of nodes that will be exceedingly difficult to manage. To help address this complexity, the third technical area of the PIPES program will focus on the creation of low-loss optical packaging approaches to enable high channel density and port counts, as well as reconfigurable, low-power optical switching technologies.
Additionally, the program will combine the advanced microelectronics capabilities of commercial industry, innovative photonics solutions from research communities, and DoD-specific application drivers from the defense industry into a framework for long-term technology availability by establishing and supporting a domestic technology ecosystem.
PIPES Researchers Demonstrate Optical Interconnects to Improve Performance of Digital Microelectronics
Under DARPA’s Photonics in the Package for Extreme Scalability (PIPES) program, researchers from Intel and Ayar Labs have demonstrated early progress towards improving chip connectivity with photons – or light.
Researchers from Intel and Ayar Labs working on PIPES have successfully replaced the traditional electrical input/output (I/O) of a state-of-the-art field programmable gate array (FPGA) with efficient optical signaling interfaces. The demonstration leverages an optical interface developed by Ayar Labs called TeraPHY, an optical I/O chiplet that replaces electrical serializer/deserializer (SERDES) chiplets. These SERDES chiplets traditionally compensate for limited I/O when there is a need for fast data movement, enabling high-speed communications and other capabilities. Using Intel’s advanced packaging and interconnect technology, the team integrated TeraPHY and the Intel FPGA core within a single package, creating a multi-chip module (MCM) with in-package optics. The integrated solution substantially improves interconnect reach, efficiency, and latency – enabling high-speed data links with single mode optical fibers coming directly from the FPGA. Built in GlobalFoundries’ advanced photonics process, the co-packaged TeraPHY chiplet used for this demonstration is capable of 2 Terabits per second (Tbps) of I/O bandwidth at a small fraction of power compared to electrical I/O.
“This early PIPES program demonstration is a big step towards enabling powerful systems that leverage the advantages of optical signaling,” said Dr. Gordon Keeler, the DARPA program manager leading PIPES. “A key goal of the program is to develop advanced ICs with photonic interfaces capable of driving >100 terabits per second (Tbps) I/O per package at energies below one picojoule per bit (pJ/bit). FPGAs with photonic interfaces will have broad impact, improving high-performance computing, artificial intelligence, large-scale emulation, and DoD-specific capabilities such as advanced radars. With this demonstration, the Intel team has made a solid step towards our goal.”
To accomplish the demonstration, Intel and Ayar Labs’ researchers leveraged technical advances achieved under two other DARPA programs – the Photonically Optimized Embedded Microprocessors (POEM) and Common Heterogeneous Integration and IP Reuse Strategies (CHIPS) programs. Now concluded, the DARPA POEM program sought to develop photonic technologies that could be integrated within embedded microprocessors to enable seamless, energy-efficient, high-capacity communications within and between the microprocessor and dynamic random access memory (DRAM). Ayar Labs’ work under POEM helped generate the first TeraPHY optical I/O chiplet.
Researchers also leveraged low-power signaling standards and chiplet packaging processes developed by Intel under the DARPA CHIPS program. To help address skyrocketing design costs and increase system flexibility, CHIPS is working to develop an ecosystem of discrete modular, reusable IP block that can be assembled into systems using various integration technologies. Critical to this effort was the establishment of a common interface standard, which Intel supplied via the Advanced Interface Bus (AIB). AIB is a publicly available, open interface standard that enables Intel and other silicon IP providers working under the program to easily build chiplets that can inter-operate with each other. The PIPES team used the AIB interface standards to integrate the MCM and in-package optics.
As PIPES progresses, the Intel team will continue to advance performance of the integrated technologies. Through the next phases of the program, all PIPES researchers will focus on enabling aggregate signaling rates to 100 Tbps and beyond, maturing various photonics technologies, and meeting demanding metrics for efficiency, latency, and bandwidth density.
DARPA asks industry for multi-wavelength lasers for next-generation optical computing, sensors, and LiDAR, in April 2021
Officials of the U.S. Defense Advanced Research Projects Agency (DARPA) in Arlington, Va., issued a small-business opportunity solicitation (HR001121S0007-07) last week for the Multi-Wavelength Laser Sources project. The goal is to develop efficient, compact, manufacturable multi-wavelength laser sources that are critical for co-packaged optical interconnects, advanced data processing, sensors, and other emerging silicon photonics applications.
The DARPA Photonics in the Package for Extreme Scalability (PIPES) program seeks to enable next-generation microelectronics with co-packaged optical I/O for future high-performance DoD and commercial systems. Short-reach optical interconnects have historically utilized a small portion of the optical spectrum, with current architectures using only one to a few wavelengths per fiber. However, as the demands on bandwidth and efficiency increase, advances in compact multi-wavelength laser sources are required to enable next-generation co-packaged photonic I/O. While the commercial availability of such technology remains elusive, this SBIR program looks to accelerate its transition from today’s laboratory demonstrations and small-scale prototyping to commercial availability, targeting metrics aligned with the needs of silicon photonics-based solutions for emerging computing applications.
The cost, form factor and performance requirements of laser sources for high-density optical interconnect and computing are radically different than those for wavelength division multiplexing (WDM) in telecommunications. A variety of approaches exist to enable sixteen or more wavelengths from a compact source, but formidable challenges exist in achieving adequate power per line, stability, and wall-plug efficiency in a convenient, volume-manufacturable product.
DARPA is soliciting scalable technical approaches to multi-wavelength laser sources that are compatible with chip-scale fabrication and integration methods. Solutions developed under this topic shall deliver multiple laser channels (≥ 16 wavelengths) on a regular frequency grid (nominally 100-800 GHz spacing) in the O-band and/or C-band of the spectrum. Such “frequency comb” sources are expected to provide milliwatt power levels or higher per channel, with all channels delivered to each optical fiber output port.
It is envisioned that the technology developed under the SBIR program will have dual-use commercial and DoD applications. In the commercial space, the laser platform will be a foundational building block for data center and high-performance computing optical interconnect. Multi-wavelength laser platforms are expected to be critical enablers for optical transport in datacom, computing, and electronic processing systems. Stable and well-calibrated comb sources may also be used in advanced sensing and spectroscopy applications. In the DoD, the multi-wavelength laser platform is anticipated to be an important building block for high-throughput interconnect in high-performance computing, edge processing, emerging artificial intelligence (AI) and machine learning (ML) systems, and sensors. Additional
DoD applications include high-bandwidth microwave photonic systems and coherent LiDAR.