Due to the growing, insatiable thirst for information, both commercial and defense communications are driving towards increasingly higher data rates and wider bandwidths of operation. This in turn is driving systems toward higher operating frequencies, which more easily supports larger channel bandwidths. For example, today’s cellular networks (i.e., cellular
networks based on 5G, the fifth-generation technology standard) operate at 6 GHz and below with development underway for 5G at millimeter wave frequencies (from 24.25 GHz to 52.60 GHz).
Now, as we look into the future, it is evident that we are slowly moving towards applications, such as virtual and
augmented reality, ultra-HD video conferencing, 3D gaming, and the use of wireless for brain machine interfaces, which will put even more strict constraints on the throughput, reliability, and latency requirements. 6G is anticipated to push to even higher millimeter-wave frequencies in pursuit of even larger channel bandwidths and higher channel capacities.
Sustaining a flexible and ubiquitously available 100 Gbps network for backhaul and access in systems beyond 5G will require the exploitation of higher frequency bands, the adoption of novel hardware technologies and advanced materials and the rethinking of Communication Theory framework and traditional design principles and architectures.
The upper millimeter-wave band, known as G-band (110 GHz to 300 GHz), represents an attractive, underutilized portion of the EM spectrum for high data rate communications applications. This band is also attractive for imaging, radar sensor, satellite crosslink and deep space communications because it can provide high resolution, smaller size, high gain and wider beamwidth. From the achievable communication channel capacity perspective, particularly appealing is the portion of G-band above 200 GHz, where a local minimum in atmospheric absorption (i.e., an atmospheric transmission window) is located.
However, adequate RF electronics does not exist today to support operation in this frequency band, particularly for size, weight and power (SWaP) constrained applications. In particular, the efficiency of G-band electronics is poor (i.e., in single digits) and must be addressed to make G-band systems viable.
Officials of the U.S. Defense Advanced Research Projects Agency (DARPA) in Arlington, Va., issued a broad agency announcement (HR001121S0042) in Sep 2021 to develop the Electronics For G-Band Arrays (ELGAR) project. The ELGAR program seeks to develop integration technologies to implement demonstration and validation circuits and test articles including compact, high-efficiency G-band power amplifier MMICs and transmit and receive array front-end test articles that operate at 220 GHz.
DARPA anticipates that the most challenging performance aspects of these MMICs and array test articles will be achieving 30 percent power amplifier power-added efficiencies, and more than 34 Watts per square centimeter transmit array power density and 24 percent transmit array efficiency at the 220 GHz operating frequency.
As has been the case for communications at lower frequencies, phased arrays and massive multiple-input multiple-output (MIMO) operation are the preferred implementation solution for millimeter-wave systems. In an array, the antenna elements and associated transmit and receive electronics are typically spaced on a λ/2 lattice grid to enable wide-angle scanning while minimizing main beam sidelobes. At G-band, the λ/2 lattice size is between 0.5 mm and 1.4 mm which places a significant constraint on the allowable physical area into which the RF electronics must fit. At the same time, data rate, range, and sensitivity are directly proportional to the amount of power that can be radiated from the array face. High data rate communication links, therefore require high output power density.
G-band arrays can be implemented using either silicon-based (e.g., CMOS, SiGe) RF integrated circuits (ICs) or III-V compound semiconductor (e.g., GaAs, GaN, InP) MMICs. Each approach has advantages but also limitations.
The dense, planar, multi-layer back end of line (BEOL) interconnects and integration technologies developed for commercial electronics have made possible silicon-based G-band RF ICs that physically fit into the λ/2 lattice. In addition, silicon technology includes compact, lowloss through-substrate vias (TSVs), micro-bump interconnects, and mature integration processes to vertically integrate silicon RF ICs with other array components using low-loss RF
interconnects. The silicon RF IC and integration technology have been used to successfully demonstrate phased arrays that operate at G-band.
On the other hand, silicon-based solutions have limited RF output power and efficiency due to the fundamental gain and breakdown voltage limitations of the silicon-based transistors. For example, from first principles calculations, the maximum achievable efficiency for a 220 GHz G-band Si transistor is ~24%. Since power amplifiers (PAs) are created by combining multiple transistors to increase output power, the transistor efficiency sets a fundamental upper limit to
the PA efficiency (~18% at 220 GHz). This theoretical limit is not achievable in practice due to losses associated with PA impedance matching and power combining networks. Consequently, the power-added efficiencies (PAE) of silicon-based G-band PAs have been limited to less than 10% for frequencies greater than 150 GHz.
Through significant investment in programs such as Sub-millimeter Wave Imaging Focal-plane Technology (SWIFT), Terahertz (THz) Electronics, and Nitride Electronic NeXt-Generation Technology (NEXT), DARPA has successfully developed III-V transistor technologies (e.g., InP, GaN) capable of overcoming the gain and breakdown voltage limitations of the siliconbased transistors at G-band. For example, due to the high breakdown field and carrier velocity
inherent in III-V materials, III-V transistors that operate at G-band (220 GHz) can theoretically achieve > 39% PAE, setting a fundamental upper limit to the PA efficiency of > 30 % . Also, III-V multi-finger transistor cells can generate an output power in excess of 40 mW at G-band, so relatively few transistor cells need be combined to achieve considerable
PA output power levels. For example, III-V based G-band PAs exceeding 200 mW of output power at 200 GHz have been demonstrated.
However, while the III-V based transistors have been scaled to support G-band operation, the BEOL interconnects and integration techniques in III-V-based technologies have not been scaled. As a result, the existing III-V fabrication processes, which typically offers only two to four non-planar on-chip interconnect metal layers, impose a fundamental limitation on the achievable performance of III-V circuits. In particular, the III-V on-chip interconnects are large and inefficient, leading to passive circuits such as impedance matching and power combining networks that are physically large and lossy. In turn, this has resulted in PA MMICs that do not physically fit within the λ/2 G-band array lattice and are severely limited to less than 10% achievable PAE for frequencies greater than 150 GHz.
As a result, novel integration approaches are needed that will make it possible to combine the superior BEOL and interconnect features of silicon-based technologies with the superior RF performance of the III-V compound semiconductor transistors in order to realize compact, efficient, G-band MMICs and array front-ends. As a part of this initiative, DARPA is interested in novel heterogeneous integration approaches that result in transmit and receive circuit
compactness needed to fit all array element electronics within the λ/2 G-band lattice spacing and enable a revolutionary increase in power density and power efficiency of MMICs and phased arrays at G-band.
The ELGAR program seeks to develop integration technologies needed to create compact, high performance III-V RF electronics to enable communication and sensing systems at G-band frequencies. These integration technologies include dense, silicon-like, on-chip BEOL and lowloss chip-to-chip interconnects. Once developed, the integration technologies will be leveraged to implement demonstration and validation circuits and test articles including compact, high efficiency G-band Power Amplifier (PA) MMICs and transmit and receive array front-end test articles that operate at 220 GHz. DARPA anticipates that the most challenging performance aspects of these MMICs and array test articles will be achieving 30% PA PAE, and > 34 W/cm2 transmit array power density and 24% transmit array efficiency at the 220 GHz operating frequency. The MMICs, array front-end test articles, and interconnects will be constrained to a λ/2 lattice spacing. The array test articles must be able to transmit and receive, at a minimum, circularly polarized signals.
To achieve these program objectives, ELGAR must overcome two (2) technical challenges:
1) Achieving efficient, compact G-band MMICs with high output power density ELGAR seeks to develop on-chip integration technologies that will simultaneously enable MMIC compaction (to increase power density), reduction in loss (to increase PAE), and minimization of mechanical stress (from compact multi-layer interconnects) while maintaining the superior RF performance of III-V transistors.
Approaches may include but are not limited to:
III-V-compatible, Si-like Cu damascene or similar planar multi-layer metal interconnects
Advanced ultra-low-k interlayer dielectrics such as porous oxides, air cavities or similar materials/structures to minimize capacitance
Novel, low-loss, compact impedance matching and combining networks enabled by the availability of more interconnect layers
Robust, on-chip capacitors (e.g., MIM caps with high-k dielectrics) with reduced footprint for use in high density on-chip bypass capacitors
Novel approaches for compacting or reducing the footprint of and loss in multi-finger III-V transistor cells (Note: Development of new III-V device epitaxial layer structures or intrinsic transistor structures is out-of-scope.)
Novel approaches for routing of bias, RF and ground lines while maintaining signal integrity and isolation in compact MMICs
2) Achieving low-loss off-chip interconnects between adjacent G-band array components.
ELGAR seeks to develop off-chip integration technologies to create compact, efficient, array front-end test articles. This may include but is not limited to:
Approaches to heterogeneously integrate III-V MMICs with non-III-V materials such as antennas and Si ICs
Approaches to minimize the size and loss of lateral and vertical DC and RF component-tocomponent interconnects while maintaining signal integrity
High-aspect-ratio III-V TSVs
Optimization of RF interconnect and TSV impedance (e.g., TSV diameter/pitch) and impedance match to transmission lines to minimize loss
Approaches that support chip-to-chip integration with micro-bumps
Approaches that support vertical 3D chip stacking
While innovation in thermal management solutions is not within the scope of the ELGAR program, the array integration approach must also take into consideration thermal dissipation of the PA. Since the output power density of the ELGAR PA and transmit array front-end test articles is higher than state of the art (SoA) due to the compact PA size, proposers are expected to develop ELGAR integration solutions that will maintain safe PA and array operating temperatures (with conventional air-cooling solutions) for reliable operation.