Demand for specialized integrated circuits for military electronics continues to surge exponentially with no end in sight. Systems that synchronize the activity of unmanned aerial vehicles; real-time conversion of raw radar data into tactically useful 3-D imagery; and instant access to high-resolution sensor feeds on the battlefield are only three examples of this reality. Despite the importance of these capabilities to national security, however, current circuit-design methods often result in devices that require more power than can be practically supplied on small flying platforms or on warfighters already burdened by too much battery weight.
It’s not that engineers are incapable of designing custom integrated circuits that can perform a specific task with optimum power efficiency. It is, rather, that they are today stymied by the prospect of spending up to $100 million and working for more than two years to complete such a design. As a result, Defense Department engineers often turn to more generic, inexpensive, and readily available general-purpose circuits, and then rely on software to make those circuits run the required specialized operations. Using general-purpose circuits can speed up design and implementation, but also burdens electronic systems with unnecessary power-gobbling circuitry. DARPA launched new Circuit Realization At Faster Timescales (CRAFT) program in 2015, with goals to reduce by 10X the effort required to design and verify complex SoCs in leading edge CMOS technology and to reduce by 5X the effort required to port designs to a new fabrication process.
“This dilemma has reduced the use of custom-integrated circuits and, consequently, the performance of DoD systems,” according to BAA of the three-phase program, Circuit Realization At Faster Timescales (CRAFT), that was slated to last just over three years with total funding of about $30 million. Overseen by Linton Salmon, a program manager in DARPA’s Microsystems Technology Office (MTO), the CRAFT program seeks to develop new fast-track circuit-design methods, multiple sources for integrated circuit fabrication, and a technology repository that will facilitate reuse of proven solutions.
Reducing the time and cost for designing and procuring custom, high-efficiency integrated circuits, should drive more of those in the DoD technology community toward best commercial fabrication and design practices,” CRAFT program manager, Dr. Linton Salmon in a program information release. “A primary payoff would be a versatile development environment in which engineers and designers make decisions based on the best technical solutions for the systems they are building, instead of worrying about circuit design delays or costs.”
Many systems could benefit from advances of the sort that CRAFT seeks to catalyze. Consider, for example, the data- and computation-intensive “Gotcha” radar system that the Air Force Research Laboratory is developing to identify moving objects over city-scale areas and render detailed 3-D imagery. “Gotcha currently requires a land-based supercomputer to make sense of the radar data and convert it into tactically useful imagery. However, relaying the data to a remote supercomputer across a contested data link can cause crippling delays,” Salmon explained. “The CRAFT program could help put more of the necessary computational power on the UAV itself or on the backs of warfighters, enabling quicker delivery of the imagery to those who need it most.”
To achieve its goals, CRAFT seeks to shorten the design cycle for custom integrated circuits by a factor of 10 (on the order of months rather than years); devise design frameworks that can be readily recast when next-generation fabrication plants come on line; and create a repository so that methods, documentation and intellectual property need not be reinvented with each design and fabrication cycle.
At the core of the CRAFT vision is an unprecedented ability to fabricate customized, technology-specific circuits using the 16 nanometer/14 nm commercial fabrication infrastructure that today produces generic commodity circuits. “A custom integrated circuit designed only to process images from an airborne radar or to analyze sensor data for warfighters on the ground doesn’t need to run a spread sheet or a word processor,” Salmon said. “Why carry around a heavy bulging Swiss Army knife when all you need is a single Phillips-head screwdriver?”
Being able to jettison the massive amounts of circuitry dedicated to everyday functions would allow the resulting spare capability to be devoted to crucial functions, Salmon continued. “In the end,” he said, “you would have a top-of-the-line, custom-integrated circuit that does only the job you need and does so much more effectively.”
“If CRAFT is successful, design of custom integrated circuits will be far more readily available to those building DoD systems,” Salmon said. “As a result, engineers will be able to make decisions based on the best technical solutions for the systems they are building, instead of worrying about circuit design delays or costs.”
The Defense Advanced Research Agency announced an $8 million contract modification for the University of Southern California’s Information Sciences Institute to work on a program that develops circuits that be quickly adapted rather than wholesale reinvented. Work will be performed by USC in Marina Del Ray, California, with an expected completion date of December 2019.
Officials of the U.S. Defense Advanced Research Projects Agency (DARPA) in Arlington, Va., announced AN $8.2 million contract modification to the USC Information Sciences Institute (ISI) in Los Angeles in Aug 2017 for phase-two options in the Circuit Realization at Faster Timescales (CRAFT) – FinFET Foundry/Design Aggregation Services military chips program.
USC ISI won an $11.8 million contract in December 2015 for the first phase of the CRAFT FinFET program. USC ISI then won $3 million in CRAFT FinFET contract options in March 2016 — $1.2 million for phase 1, $890,524 for phase 2 option 1, and $840,335 for phase 3 option 2.
The CRAFT FinFET program seeks to develop a custom IC design flow to reduce the effort necessary to design high-performance custom ICs; help port IC designs to secondary IC foundries and more advanced technologies; and reuse of IC intellectual property.
In the program’s first phase USC experts will have demonstrated a 10X reduction in design efforts using a standard flow for a system-on-chip (SoC) with logic block size of more than 200,000 gates; several mixed signal blocks, SRAM memory blocks, and third-party intellectual property (IP) blocks.
In the second phase, USC experts will demonstrate a 7X reduction in design efforts to create a DARPA-selected SoC design, document the design flow; test fabricated chip functionality across standard temperature ranges; characterize an initial suite of macros and generators; document a reference CAD flow; and design a suite of macro and generators.
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