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DARPA’s SAHARA to automate Structured ASICs production and enhance their security for defense electronic systems

Time to market demand has forced integrated circuit design, manufacturing and testing to be done at different places across globe. This approach has led to numerous security concerns like overbuilding of chips from foundries, IP protection, counterfeiting and hardware Trojans. Hardware Trojans (HT), which are malicious circuit inclusions into the design from an adversary with an intention to damage the functionality of the chip at a much later date or leaking confidential information like keys used in cryptography.


DARPA  announced in March 2021, the Structured Array Hardware for Automatically Realized Applications (SAHARA) program, which aims to expand access to domestic manufacturing capabilities to tackle challenges hampering the secure development of custom chips for defense systems. Working in partnership with Intel and academic researchers from University of Florida, University of Maryland, and Texas A&M, SAHARA will leverage leading-edge, U.S.-based manufacturing capabilities to enable the automated and scalable conversion of defense-relevant field-programmable gate array (FPGAs) designs into quantifiably secure Structured ASICs. The program will also explore novel chip protections to support the manufacturing of silicon in zero-trust environments. A reliable, secure, domestic source of leading-edge semiconductors remains critical to the U.S.


SAHARA is a critical program supporting the Department of Defense (DoD) microelectronics Roadmap led by the Under Secretary of Defense for Research and Engineering – USD(R&E) – to define, quantify, and standardize security while strengthening domestic semiconductor manufacturing. The Rapid Assured Microelectronics Prototypes-Commercial (RAMP-C) and State-of-the-Art Heterogeneous Integration Prototype (SHIP) projects are also integral to the DoD Roadmap.


While FPGAs are widely used in military applications today, Structured ASICs deliver significantly higher performance and lower power consumption, which makes them an efficient and effective alternative for defense electronic systems. In a FPGA, interconnects and logic blocks are programmable after fabrication, offering high flexibility of design and ease of debugging in prototyping. However, the capability of FPGAs to implement large circuits is limited, in both size and speed, due to complexity in programmable routing, and significant space occupied by programming elements, e.g. SRAMs, MUXes. On the other hand, ASIC design flow is expensive. Every different design needs a complete different set of masks. The Structured ASIC is a solution between these two. It has basically the same structure as a FPGA, but being mask-programmable instead of field-programmable, by configuring one or several via layers between metal layers. Every SRAM configuration bit can be replaced by a choice of putting a via or not between metal contacts.


A number of commercial vendors have introduced structured ASIC products. They have a wide range of configurability, from a single via layer to 6 metal and 6 via layers. Altera’s Hardcopy-II, eASIC’s Nextreme are examples of commercial structured ASICs.  Intel® eASIC™ devices are structured ASICs, an intermediary technology between field-programmable gate arrays (FPGAs) and standard-cell ASICs. These devices provide lower unit-cost and run on lower power compared with FPGAs and provide a faster time to market and lower non-recurring engineering cost compared with standard-cell ASICs.


Intel will use its structured ASIC technology to develop platforms that significantly accelerate development time and reduce engineering cost compared to traditional ASICs. Intel will manufacture these chips using its 10nm process technology with the advanced interface bus die-to-die interconnect and embedded multi-die interconnect bridge packaging technology to integrate multiple heterogenous die in a single package.


Manually converting FPGAs to Structured ASICs, however, is a complex, lengthy, and costly process, making it difficult to justify the economic burden at the volume of custom chips required by DoD applications. Further, current conversion processes do not address design security considerations. To dramatically shorten the design process, reduce associated engineering costs, and enhance chip security, the Intel team will work to automate the conversion process for both currently fielded FPGAs as well as future capabilities, while adding unique chip protections to address supply chain security threats.


SAHARA aims to dramatically shorten the ASIC design process through automation while adding unique security features to support manufacturing of the resulting silicon in zero-trust environments. “SAHARA aims to enable a 60 percent reduction in design time, a 10X reduction in engineering costs, and a 50 percent reduction in power consumption by automating the FPGA-to-Structured ASICs conversion,” said Serge Leef, a program manager in DARPA’s Microsystems Technology Office. “The partnership with Intel will ultimately afford the DoD with significant cost and resource savings while enabling the use of leading-edge microelectronics across a host of applications.”


Additionally, Intel aims to establish domestic manufacturing capabilities for the Structured ASICs on their 10nm process. The partnership enables the use of leading-edge foundry capabilities for the development of secure military electronics – something not currently available on-shore.


To bolster chip security, SAHARA is also exploring security countermeasures capable of thwarting reverse engineering and counterfeiting attacks. The research teams aim to develop novel chip protections and employ verification, validation, and red teaming to stress test the resulting measures. Once proven, it is anticipated that the countermeasures will be integrated into Intel’s Structured ASIC design flow.


In collaboration with the University of Florida, Texas A&M and University of Maryland, Intel will develop security countermeasure technologies that enhance protection of data and intellectual property from reverse engineering and counterfeiting. University teams will use rigorous verification, validation and new attack strategies to test the security of these chips. The security countermeasure technologies will be integrated into Intel’s structured ASIC design flow.


“The structured ASIC platforms and methods developed in SAHARA together with the advanced packaging technology developed in SHIP will enable the U.S. Department of Defense to more quickly and cost effectively develop and deploy advanced microelectronic systems critical to DoD modernization priorities,” said Brett Hamilton, deputy principal director for Microelectronics in USD(R&E).


As the sole U.S.-based advanced semiconductor manufacturer, Intel promotes supply-chain security by utilizing facilities within the U.S. to manufacture, assemble and test custom chips for the SAHARA partnership.


“We are combining our most advanced Intel® eASIC structured ASIC technology with state-of-the-art data interface chiplets and enhanced security protection, and it’s all being made within the U.S. from beginning to end. This will enable defense and commercial electronics systems developers to rapidly develop and deploy custom chips based on Intel’s advanced 10nm semiconductor process.”
–José Roberto Alvarez, senior director, CTO Office, Intel Programmable Solutions Group



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