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Silicon photonics manufacturing overcoming challenges to meet requirements from 5G wireless, data centres to supercomputers, biosensing to Quantum Optics

Silicon has been the mainstay of micro-nanoelectronics since the late 1950s, being widely adopted for electronic devices and complementary metal oxide semiconductor (CMOS) technologies. In the early 2000s, silicon material’s broad transparency that spanned the short- and mid-wavelength infrared enabled silicon-based optics to blossom into a wide variety of photonics technologies that targeted applications in data communications, sensing, and advanced computing.


The intrinsic capability of light to transmit signals with low latency and power dissipation, at ultrahigh data rates, can be scaled from backbone infrastructures to rack-level optical links, down to chip-to-chip photonic interconnects. The silicon photonic technology is emerging in the datacom and telecom industries replacing copper wires with fiber optics and silicon photonic interfaces. Utilizing light-based communication between chips, or in self-contained modules, ultimately could have a big impact on chip design. Photons moving through waveguides are much faster than electrons in copper wire, and it takes far less power to drive optical signals than electrical signals. In addition, there is literally an entire spectrum of options available using light, most with negligible heat dissipation.


In optical communications, for example, the progressive adoption of power-efficient, high-speed, silicon photonic links has helped to address the growing demand for data transmission bandwidth and increase computing capabilities. Optical coherent communication, in which both the amplitude & relative phase of light is used to pack more information per unit bandwidth in a physical optical channel, is becoming the dominant method in terrestrial networks , and greatly benefits from chip-scale integration of the multi-branch modulators, mux/de-mux circuits, and detectors, says Xiaoxi Wang, University of California, San Diego.


However, silicon could not meet the necessary requirements of these integrated optics applications without the additional innovation of silicon-on-insulator (SOI) technology. The SOI material platform offers considerable advantages by leveraging the highly mature ecosystem of CMOS technology, as well as comparatively newer processing technologies that enable the transfer of very thin layers of material from one substrate to another. The so-called Smart Cut process, collaboratively developed by CEA-Leti and SOITEC, underlies the development of engineered wafers by stacking extremely thin (from 10 nm up to a few hundred nanometers) and perfectly uniform crystalline layers of semiconductors that could not be achieved using classic microelectronic technologies. Based on this process, SOI technology can now replace traditional copper lines in data interconnects with submicrometer-wide silicon waveguides that send, receive, and process information using optical frequencies, write Céline Cailler and others from SOITEC


Furthermore, thanks to its inherent CMOS-compatibility, the SOI platform provides a cost-effective approach for optical chip design and high-volume manufacture that features scalable bandwidth, footprint, and functionality. Beyond optical transceivers for the data center interconnect (DCI) market — which is today the technology’s most mature segment — SOI photonics is also enabling applications in novel computing architectures, Internet of Things (IoT) components, biosensors, and lidar systems. It will soon support advancements in quantum technologies. By leveraging mature semiconductor manufacturing methods, engineered wafers that incorporate SOI technology offer a powerful approach toward broader adoption of integrated optics.


Manufacturing technologies

By leveraging mature semiconductor manufacturing methods, engineered wafers that incorporate SOI technology offer a powerful approach toward broader adoption of integrated optics.

Figure 2. A schematic view of a photonic SOI substrate (a). A tilted scanning electron microscopy view of a silicon waveguide fully etched into the top silicon layer (b). A cross-sectional SEM image of a twin-waveguide directional coupler etched into the top silicon layer (c). Courtesy of CEA-Leti.

Basically, high-quality single-crystalline silicon layers ranging in thickness from a few nanometers to several microns can be transferred onto a buried oxide (BOX) layer that is wet-grown onto a silicon handle substrate. In photonics applications, the BOX layer ensures high optical isolation, passivation of surface states, and extremely low defect density, while the handle substrate provides mechanical stability. Notably, such manufacturing methods can scale SOI technology to 200- and 300-mm wafer formats to combine high-throughput manufacturing capability with standard CMOS processing, enabling the integration of digital and photonic functions.


Additionally, the Smart Cut process allows further integration of advanced materials on silicon and other substrates. These materials include germanium on insulator, group III-V compounds such as gallium arsenide and indium phosphide, and piezoelectric materials such as lithium tantalate or lithium niobate. All pave the way to optical systems that offer high-performance emission, modulation, or detection of light along with industrial scalability.

Figure 4. Top-layer silicon surface roughness measured with 30- × 30-µm atomic force microscopy scans, showing SOI evolution over the last few years. Today, processing technology can deliver 300-mm photonic SOI wafers with angstrom-level hill-to-valley surface roughness, providing cutting-edge material quality to integrated optics applications. Courtesy of SOITEC.

SOI technology is still evolving today to offer new capabilities for silicon photonics. For example, control over the thickness of silicon layers  has continuously improved to allow greater uniformity within a few nanometers and provide ideal optical behavior at both the device and circuitry levels. Similarly, silicon layer surface roughness  can be controlled at the atomic scale to minimize unwanted scattering and to stabilize waveguide index and the phase of optical signals. These properties are essential for low-loss and high-coherence applications, such as quantum silicon photonics or solid-state chip-based lidar.


With regard to manufacturability, the geometrical aspects associated with SOI wafers are also of critical importance. Managing the warp and bow of SOI substrates is essential in foundry equipment, including etching and lithography tool sets used for defining submicrometric silicon features. Maintaining all of these SOI specifications is instrumental to controlling process window stability and optimizing fabrication yields for silicon photonics.


Reaching the core

With the advent of 5G networks, the steady growth of data traffic in today’s telecommunications infrastructures is driving increases in both transmission rates and computing capabilities. Such a burst in data is challenging the ability of short-reach copper-based interconnects in data centers and server architectures to offer enough bandwidth at reasonable power dissipation. Optics-based telecommunications has the potential to solve this challenge, if photonic function­alities can be integrated on electronic chips and cards to help trigger the onset of a photonics-based computational era.


Silicon photonic integrated circuits would pave the way toward a new framework for optoelectronics that offers a significant integration potential with cost-effective CMOS electronics. Moreover, the strong refractive index contrast between silicon and silicon dioxide (n ~ 2) offered by the SOI material platform enables flexible implementation of multiple optical functions within small footprints. The index contrast offers the potential to integrate devices such as waveguides and resonators, semiconductor lasers and amplifiers, chip-to-fiber couplers, high-speed modulators, and silicon germanium photodetectors, as well as filters and wavelength (de)multiplexers.


Silicon photonics pluggable transceivers have contributed to the exponential growth of cloud services. The introduction of co-packaged on-board optics further promises to usher in a new wave of disruptive advancements in artificial intelligence at the network edge and in high-performance computing. This more recent development is on track to unfold this year, according to industrial players in datacom. In fact, inherent limitations in the copper-based serializer/deserializer (SerDes) technology used for data input/outputs (I/Os) in today’s server switching cores will fuel further interest in shifting optics down to the core of electronics.


Silicon Photonics ICs (PICs) challenges

While we certainly have had successes over the past decade, why haven’t silicon photonics ICs (PICs) been more readily adopted on a larger
scale? With all their advantages (transmission speed, low power usage, older proven processes, etc.), combined with the cost efficiencies of silicon wafer production, why haven’t they taken over the market yet?


Chris Cole, VP of Advanced Development at II-VI, challenges the expectation of a wide-spread replacement of copper wires with silicon photonic interfaces. During his keynote at DesignCon 2020, Cole went so far as to call this expectation a myth. The original goal of optical fiber and related silicon photonic chips was to overcome the limitations of copper wires and support faster interconnects between data centers. To achieve this goal, data center need optical elements such as cheap lasers, low signal lose technologies (low SNR) and cheap system assembly and packaging.


Unfortunately, there is reason to doubt that silicon photonics can meet those needs. First of all, silicon is an indirect band-gap semiconductor, so it’s a lousy light amplifier, explained Cole. This reason, in turn, made Si lasers extra lousy as light amplifiers, (remember that the LA in Lasers stands for Light Amplification). Further, silicon photonics has higher signal/data loss than other technologies like free space optics. Finally, while silicon photonics packaging has been comparable in cost to conventional packaging, it has only just been on par without any additional motivating factors to improve its viability.


The shortcomings of silicon photonics lead Cole to capture two myths for the value of silicon photonics in the data room. The first myth was that silicon photonics is low in cost. But Cole argued that this technology is actually expensive when all costs are properly accounted for such as the process development, components development, modeling, mask creation, testing, yield improvement, and other expenses. While it may be true that silicon photonics has a decent cost if there as very high chip yield, the yield itself typically has many pitfalls.


In conclusion, Cole summarized that quad channel silicon photonic transceivers fundamentally have no advantage over conventional quad transceivers. The current stampede of 400G DR4 QSFP-DD SiPh transceiver designs from Intel, Cisco/Luxtera, Cisco/Acacia, Elenion, (Finisar before dropping out), and other smaller companies will result in no ROI on investment. In other words, “me too” products don’t bring market success.


The basic answer: the scaling enabled through silicon foundries is built on and tailored to transistor-based technologies.  Foundries have a lot of experience and success tied into the Moore’s Law model of ICs resulting  in the standardization and optimization achieved by ICs. We need to overcome inertia to replicate the machine that is the fabless infrastructure to work for a photonics-based world. This is easier said than done, of course.


Let’s consider what a fabless IC team receives from their foundry when designing a system-onchip (SOC). First, there is the PDK. The PDK essentially represents an implied contract that the appropriate electronic design automation (EDA) software tools, if used appropriately, will work to enable a manufacturable, operable design in the target process. At the heart of the PDK are the design rules, which define the manufacturing requirements for physical layouts. Design rule checking (DRC) ensures that the geometries created in a layout can be successfully manufactured in the given foundry process. To support the design rules, the foundries must also declare which layers on an incoming GDS or OASIS file are used for which process steps used to create the appropriate masks.


The next part of the PDK is the device models. Foundries are experts at transistor science. They meticulously characterize exactly how a transistor will perform in a given construct. As long as the designers build the transistors correctly, they can have confidence that the devices will perform as designed. However, device models alone are insufficient for scaling. If designers had to focus on making sure every single transistor in the layout was assembled correctly, it would take eons to design the multi-billion transistor SoCs that we create today. To enable this scaling, the PDKs add more information. First are pre-characterized cells (Pcells). Pcells allow the designer to select among a set of known and allowed parameters that can be modified within a range to enable different electrical behaviors for a transistor or a set of


Unlike the transistor, for which the electrical behavior is largely characterized by width and space, it is far more difficult to verify the intended electrical behavior of an optical device based on its layout, or even silicon image, without doing full simulation. Fortunately, that may not be necessary. The idea behind LVS device verification is to assure that the layout adequately represents the intent. An alternative approach is simply to re-render the intentional shape to the placement in context. If no changes are found, then designers know the placed device matches the intended device. There are several approaches that can be used for this comparison, from complex pattern matching to simply regenerating based on the optical equations.


Of course, even that is not enough. To go further, the foundries also provide pre-characterized standard cell libraries. These libraries represent commonly used logical gates and other relatively simple building blocks. The foundries also provide larger IP blocks and/or characterize and approve IP from 3rd-party providers for components like memories, processors, etc. Theoretically, SoC designers can combine any or all of these to their liking, and be confident in their behavior and performance.


It means that the development of similar tools and components are essential to integrating PICs into the traditional IC design and verification processes, starting with the development of a photonics PDK. Actually, despite the challenges, there has been good progress towards achieving this goal. Despite the fact that the GDS and OASIS file formats do not natively support the curved structures common in PICs, and that traditional DRC verification of these structures results in thousands of false errors, we have successfully enabled methods that allow a dedicated DRC run to check PIC layouts for real layout problems without flagging false errors.


We are not yet at a point of having true pre-characterized photonics devices complete with a Pcell definition, but we are close. The ability to create such Pcells can be achieved through the use of Python™-based Pcells (Pycells), or by using tools like the PhoeniX OptoDesigner design
platform or Luceda IPKISS.eda design framework . Calibre® nmLVS™ circuit verification can perform simple device black box style layout vs. schematic (LVS ) verification to ensure no shorts or opens exist in the generated layout, and pass the rendered optical design as extracted
from the layout to optical simulators such as Lumerical’s Interconnect circuit design tool .


The second myth was that silicon photonics is like any other CMOS ASIC chip in terms of development and cost. To counter this myth, Cole argued that the two largest ASIC CAE companies (e.g., Synopsys and Cadence) had revenues (~$5.5B) similar to the entire Datacom optics industry. Further, the true cost of just developing process design kits (PDKs) for advanced CMOS nodes is comparable to the entire R&D budget of an optical transceiver vendor.


While CMOS tool predictability enables a first pass success for complex ASICs, silicon photonic tools do not predict final product performance. Equally problematic is that the assembled and packaged silicon photonic performance is not modeled. Finally, successful design efforts require device and process engineer’s expertise for those companies developing silicon photonic chips.


But there is still one last issue to consider—how to successfully combine photonics and electronics components. In the ideal case, designers would put the required electrical and photonics components together on the same die. But, photonics components are generally quite large, compared to their electrical cousins, and they do not need or use advanced node processes. If designers need electronics capabilities that are only enabled by advanced nodes to drive the photonics components, they would end up using lots of very expensive area for the photonics components, making the final SOC price-prohibitive. In fact, given the large size of photonics components, trying to combine them with electronic components on one chip may also drive the die size up, increasing the costs even more.


Recent advances

The obvious solution here is multi-die packaging, and the news in that regard is quite good. A great deal of progress has been achieved with foundries and outsourced assembly and test (OSAT) companies alike in the development of PDK-like approaches to simplify and reduce the
risks of package design and verification. In fact, TowerJazz, a leading-edge foundry in silicon photonics production, recently released its initial silicon photonics PDK based on the industryleading Calibre nmPlatform. With Calibre nmPlatform s upport, customers targeting TowerJazz’s PH18 silicon photonics process now have the same high level of confidence that they are constructing physically-correct silicon photonics devices as they have always had for complementary metal-oxide-semiconductor (CMOS) devices


“There’s a huge development effort, and there are now many tools available on the packaging and foundry side,” said Erik Rasmussen, an analog ASIC designer at Delta Microelectronics. “There are different foundries that provide different diodes for different wavelengths. You can get them optimized for all kinds of things. So now we have a full toolbox, which means you can play around with this for much lower cost. All the development for mechanics and packaging and process are in place. Most things are in place. So now we have a huge toolbox and we can start using to do interesting applications.”


According to Yole Développement, the silicon photonics market is expected to reach $4 billion in 2025. Market research firm LightCounting estimates that 400GbE transceiver revenues in the datacom market, which includes DCI transceivers, will reach $12 million within the same time span.


At a later stage, SOI photonics could contribute to the paradigm shift in data center architecture by introducing “fiber-to-the-processor” optical chiplets (opto-chiplets). Such novel rack-scale computing architectures would make data centers more flexible, allowing them to pool resources by using fast, low-latency optical I/Os between CPUs, ASICs (application-specific integrated circuits), storage, and memory blocks. In this sense, the adoption of optics-based I/Os will ultimately provide server architectures with greater system flexibility, scalable speeds, and cost-effective operations that only CMOS-compatible SOI photonics can deliver.


The progressive adoption of opto-chiplets based on silicon photonics would reinforce these trends. It is therefore not surprising that silicon photonics is increasingly perceived as a strategic asset by a growing number of equipment manufacturers and cloud service end users, including tier-one players in data communications technology. Electronics chipmakers and major foundries worldwide are extending their positions to master the design and processing of photonic components using SOI-based wafer technology on both 200- and 300-mm wafers. Additionally, to support high-data-rate optical communications and advanced computing applications, the industry is collaborating on a set of specifications for new high-capacity communications standards to ensure a unified supply chain.


COSMICC project leverages silicon nitride for 100-Gbps optical module  reported in June 2020

Members of a European consortium developing silicon photonics technology say they have demonstrated a fully packaged transceiver module with a data transfer rate of 100 Gb/s. Members of the EU H2020 COSMICC (CmOs Solutions for Mid-board Integrated transceivers with breakthrough Connectivity at ultra-low Cost) project have demonstrated a fully packaged 2×50-Gbps CWDM optical transceiver module that leverages broadband, temperature-insensitive silicon nitride (SiN) multiplexing components on silicon (Si), the integration of hybrid III-V/Si lasers on the Si/SiN chips, and a high-count adiabatic fiber-coupling technique via SiN and polymer waveguides. According to project member CEA-LETI, the approach offers a path toward low-cost, low-power, reduced complexity optical engines for data center and supercomputer applications requiring capacity beyond terabits per second.


SiN is 10X less sensitive to temperature than silicon, say the project members. Use of the technology can therefore significantly reduce transceiver cost and power consumption by eliminating the need for temperature control through reduced heat output. The CWDM module features a silicon photonic chip that integrates 50-Gbps NRZ optical modulators and photodetectors, and a two-channel CWDM multiplexer and demultiplexer. The control electronics exhibits an optimized energy consumption level of 5.7 pJ/bit per channel at the 50-Gbps data rate.


Led by CEA-Leti in France, the COSMICC (CmOs Solutions for Mid-board Integrated transceivers with breakthrough Connectivity at ultra-low Cost) project team believes that the new optical hardware will meet the communications industry’s demands for high-speed data modules – at a cost they say cannot be achieved with conventional approaches. The COSMICC transceiver multiplexes two wavelengths at 50 Gb/s, and will be aimed initially at applications in data centers and supercomputers.


According to CEA-Leti, the COSMICC team has in fact developed all the building blocks required to deliver faster transmission rates of 200 Gb/s and beyond, without any need for temperature control, by multiplexing four wavelengths and aggregating a large number of fibers. “This demonstration opens the way to technology that allows a reduction in the cost, power consumption, and packaging complexity – and opens the way to reaching a very high aggregated data rate beyond terabits per second,” announced the research agency. CEA-Leti scientist Ségolène Olivier, who coordinated the project, said that the critical breakthrough was the development of modulators and germanium photodetectors operating at 50 Gb/s, and their co-integration with control electronics.


“The new building blocks are essential for addressing the need for terabit-per-second transceivers at low cost and low energy consumption to sustain the exponential growth of data traffic in data centers and in high-performance computing systems,” she explained, suggesting that the technology would “answer tremendous market needs” with a target cost-per-bit that cannot be met with standard optical transceivers.


According to the COSMICC project’s official summary report, although current optical transceivers based on VCSELs are able to meet cost demands, they suffer from limited speed and reach. On the other hand, modules with indium phosphide lasers are fast but expensive. Aside from developing the two-channel 100 Gb/s transceiver module, the consortium created a new low-cost optical packaging scheme based on single-mode Si/SiN/polymer waveguide coupling that is able to combine up to 24 optical fibers, providing aggregate speeds in the terabit-per-second realm. “The implemented adiabatic coupling scheme will enable a reduction of the energy per bit of 40 per cent at 50 Gb/s compared to the grating coupler scheme,” states the project summary, adding that the team has set up a pilot line for single-mode polymer packaging substrates. CEA Leti says that the new approach consumes only 5.7 picojoules per bit for each channel operating at 50 Gb/s.


The COSMICC project funded by the European Union’s Horizon 2020 programme, was launched with objective to combine CMOS electronics and silicon photonics with innovative high-throughput fibre attachment techniques. The COSMICC project – whose name stands for ‘CMOS solutions for mid-board integrated transceivers with breakthrough connectivity and ultra low cost – brings together 11 partners from five countries, with contributions from the likes of STMicroelectronics, University of St Andrews and the University of Southampton.


“While there are already some commercial products that support 100Gbit/s communications, we need to prepare for the next generation – for example, devices that can support 400Gbit/s and 1Tbit/s, as well as developing technology that can aggregate data rates beyond 1Tbit/s.” In particular, the COSMICC project is looking to develop technology with a cost/bit that cannot be achieved using the current wavelength division multiplexing approach, said Dr Ségolène Olivier acting as project leader. In its roadmap, the COSMICC project is looking to meet a cost target of €0.15/Gbit/s, while consuming just 2pJ/bit. By contrast, today’s technology costs something like €20/Gbit/s, while consuming 35pJ/bit.


Despite anticipated developments in photonics technology, the COSMICC project is planning to use four wavelengths to achieve its target data rates. “We’ll be targeting four wavelengths using coarse wavelength division multiplexing (WDM),” Dr Olivier explained, “and each wavelength will be 20nm apart.” The project is also looking to use what she called a ‘large number of fibres’. “Until now,” she continued, “we have been limited to using four fibres. We want to increase this to 12 for transmission and a further 12 for reception. However, this will need new packaging techniques to be developed in order to allow the fibres to be attached to the photonic IC.” But data rates is only one of the challenges which COSMICC is addressing. “There is also the need to reduce power consumption,” Dr Olivier pointed out. “That will be a big challenge because the power requirements of next generation data centres will be stringent.”


One of the major consumers of power is the optical modulator. “We will need to make them more power efficient,” she continued, “and smaller, so they take up less space.” A further complication is the need for robust components, particularly when it comes to temperature. “We don’t want to have to integrate a temperature controller into the devices because it would be too expensive,” Dr Olivier noted. “So we need to enhance existing technology by introducing silicon nitride – something which will be new to photonics.” The benefit of silicon nitride is that it is ten times less sensitive to temperature than silicon. “But we will face a challenge when it comes to integrating lasers in order to reduce the global energy consumption of photonics ICs.” Dr Olivier said the need to integrate more wavelengths also needs to be explored. “We’ll need other materials for that,” she claimed, “so we will have to develop a III-V hybrid on silicon.” By combining CMOS electronics and silicon photonics with high throughput fibre attachment techniques, the COSMICC project believes it will be able to develop solutions that can scale to meet the future requirements of data centres and supercomputers.

The Silicon Photonics Applications Space. Courtesy of SOITEC.

The Silicon Photonics Applications Space. Courtesy of SOITEC.

Sensing and advanced computing

Beyond the datacom market, the benefits of silicon photonics are helping to address new applications within the sensing and advanced computing sectors. Chip-scale optical sensing can offer considerable advantages over bulky conventional solutions that rely on the expensive heterogeneous assembly of multiple, discrete components. The rising demand for advanced driver assistance systems and autonomous vehicles in the automotive, transportation, and industrial robotics markets is increasing demand for inexpensive, industrially scalable optics-based solutions. Such solutions combine the capability of photons to sense and quantify information about the physical world without suffering from electromagnetic interference or other detrimental effects typically associated with radio-frequency waves. Moreover, SOI photonics offers a more advantageous sensing platform that monolithically integrates hundreds of devices onto the same chip. Chip-scale solid-state lidar technology is another significant driver for SOI photonics development.


With regard to biosensing technology, advanced semiconductor microfabrication allows for the miniaturization of lab-on-a-chip components. Such developments have allowed silicon-based optical biosensors to make significant progress in point-of-care diagnostics. SOI photonics will contribute to these trends by supporting development of evanescent field biosensing technologies that incorporate interferometers, Bragg gratings, micro-cavities, and photonic crystal-based waveguide sensors.


SOI-driven photonic platforms can also support a broad panel of sensing mechanisms for analyte inspection based on real biomarkers for label-free detection. Lab-on-a-chip photonic sensing platforms further enable monolithic integration of optical devices, microfluidic delivery channels, and readout equipment. These applications for system-level chip packaging collectively illustrate the potential to industrialize low-cost, high-yield, portable biosensing platforms by leveraging CMOS processes.


Lastly, when it comes to advanced computing, integrated photonics is increasingly seen as an attractive platform for quantum information processing. In quantum cryptography, for example, photons can act as vectors of information due to their long coherence times at room temperature and their ability to be transmitted over existing optical fiber infrastructures. Quantum correlation of photon pairs via time-energy entanglement has already been demonstrated on the SOI platform via silicon ring resonators. Combined with the large effective nonlinearities achievable in SOI waveguides, this would allow the reduction of an emitter’s footprint by orders of magnitude over non-photonics-based sources.


To enable and support the industrialization and adoption of silicon photonics, SOI technology will need to address key challenges, such as ensuring cutting-edge material quality and supporting high- volume manufacturability. The decades-long optical age of silicon has shown that material technology and industrial success cannot run separately. This is why continued advancements in SOI technology are critical to maintaining market penetration for silicon photonics, trigger­ing future waves of photonics-based innovation and technologies.



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