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Software Defined Radio (SDR) technology

A radio is any kind of device that wirelessly transmits or receives signals in the radio frequency (RF) part of the electromagnetic spectrum to facilitate the communication or transfer of information. Software-defined radio (SDR) is a radio communication system where components that have been traditionally implemented in hardware (e.g. mixers, filters, amplifiers, modulators/demodulators, detectors, etc.) are instead implemented by means of software or firmware operating on programmable processing technologies.

 

The motivation behind SDR-based systems is reprogrammability and ease of maintenance. This technology increases the lifespan of radio communication infrastructure by allowing new protocols to be supported through software updates. Another advantage of SDRs is reduced development time and cost.

 

During the last decade, Software-Defined Radios have become the state-of-the-art for the
prototyping and implementation of communication systems in the field of terrestrial communications. Their popularity and utilization are increasing also in the aeronautical and space applications

 

SDR is the underlying technology behind the Joint Tactical Radio System (JTRS) initiative to develop software-programmable radios that can enable seamless, real-time communication across the United States military services, and with coalition forces and allies. The functionality and expandability of the JTRS is built upon an open architecture framework called the Software Communications Architecture. The JTRS terminals must support dynamic loading of any one of more than 30 specified air-interfaces or waveforms that are typically more complex than those used in the civilian sector.

 

SDR Technology

The SDR paradigm flexibility relies on the digital implementation of communications algorithms and on the availability of programmable wideband RF transceivers that integrate all the necessary functions in one chip.

 

SDR technology is crucial to the future success of wireless technology involving multiple applications, from digital IF and baseband processing to coprocessing and military communications. SDR enables wireless devices to support multiple air interfaces and modulation formats via a reconfigurable hardware platform across multiple standards.

 

One key performance parameter of SDRs is their high throughput, which is the rate of data that can flow through the system. The high throughput is enabled by the wide-band connections that SDRs can support, as well as the FPGA used to interface with the host system.

 

High-throughput SDRs find their applications in time-critical applications such as telecommunications, military, and public safety. In telecom applications, a high instantaneous bandwidth means more users and more data can be transferred over the links. In military applications, radar systems require complex signal processing to resolve geographical positions. Analysis of the signals is a time-critical task that must be done concurrently with data collection, hence requiring higher throughput to support both tasks.

 

Figure 1: Software Defined Radio Diagram from https://upload.wikimedia.org/wikipedia/commons/2/22/SDR_et_WF.svg

SWDefinedRadioDiagram

SDR Architecture

An idealized SDR would include several “hard” or fixed components including an Antenna, front-end RF Hardware, and an ADC or DAC, while the rest of the functionality would be implemented in a “soft” or programmable medium.  The most common “soft” device is a general purpose processor, but processors lack the I/O bandwidth and processing capabilities necessary for implementing SDRs for all but the simplest architectures.

 

Thankfully well architected FPGA systems can provide both the I/O bandwidth necessary and the processing capabilities needed for implementing complex SDRs, and they can do so at multi-GHz sampling rates and GHz-range bandwidths. The development of High-Level Synthesis (HLS) and code generation tools have helped the effort reduction for FPGA design. FPGAs, with their flexible design functionality and device reconfigurability, are playing a key part in bringing this SDR technology to fruition.

 

FPGAs are digital devices, so for a receiver the FPGA input would come from an Analog-to-Digital Converter (ADC) as shown below. A typical process would start with a mixer that rotates the signal intermediate frequency (IF) to DC, would flow through a filter-and-decimation process to reduce the bandwidth to that of interest, and might conclude with demodulation, energy detection, storage, or other processes.

 

However, current-generation, wideband data converters cannot support the processing bandwidth and dynamic range required across different wireless standards. As a result, the A/D converter and D/A converter usually operate at Intermediate Frequency (IF). Separate wideband analog front ends execute subsequent signal processing to the Radio Frequency (RF) stages, as shown below.

 

SDR Transmitter

SDR transmitter consists of baseband modules such as FEC encoder, modulation, IFFT etc. The digital IF is converted to analog IF using DAC (D/A converter). Analog IF is converted to analog RF and is being amplified using Power Amplifier (PA) before transmission by antenna into the air.

 

The digital baseband part is coded in DSP which provides I/Q data as per different transmitter need. This is digitally upconverted using DUC (Digital Up Conversion) with the use of digital LO (Local Oscillator) and digital mixer. The digital IF samples are converted to analog IF signals. This analog IF (Intermediate Frequency) is converted to analog RF (Radio Frequency) using RF up-converter. The RF signal is amplified before being transmitted over the air using the appropriate antenna as per desired system operating frequency.

 

SDR transmitter architecture

Digital up converter

In digital up conversion, the input data is baseband filtered and interpolated before it is quadrature modulated with a tunable carrier frequency. To implement the interpolating baseband Finite Impulse Response (FIR) filter, a proprietary FIR compiler can build optimal fixed or adaptive filter architectures for a particular standard through speed-area tradeoffs.

 

An accompanying Intellectual Property (IP) core can generate a wide range of architectures for oscillators with spurious-free dynamic range in excess of 115 dB and very high performance. Depending on the number of frequency assignments to support, the right number of digital up converters can be easily instantiated in a Programmable Logic Device (PLD).

 

Crest factor reduction

3G Code-Division Multiple Access (CDMA)-based systems and multi-carrier systems such as Orthogonal Frequency Division Multiplexing (OFDM) exhibit signals with high crest factors (peak-to-average ratios). Such signals drastically reduce the efficiency of PAs used in the base stations. Proprietary FPGAs offer a reconfigurable platform for SDR base stations to implement Crest Factor Reduction (CFR) techniques customized to each standard.

 

Digital predistortion

The 3G standards and their high-speed mobile data versions employ non-constant envelope modulation techniques such as Quadrature Phase-Shift Keying (QPSK) and Quadrature Amplitude Modulation (QAM). This places stringent linearity requirements on the power amplifiers. Digital Predistortion (DPD) linearization techniques, including both Look-Up Table (LUT) and polynomial approaches, can be efficiently implemented using high-performance FPGAs. The multipliers in the DSP blocks reach speeds up to 380 MHz and can be effectively time-shared to implement complex multiplications. When used in SDR base stations, these FPGAs can be reconfigured to implement the appropriate DPD algorithm that efficiently linearizes the PA used for a specific standard.

 

SDR Receiver

The first module is RF tuner. This RF tuner converts RF signal to amplified IF signal. It replaces  three modules (RF amplifier, mixer, IF amplifier) of traditional analog receiver. After that A/D converter converts analog IF into digital IF samples. The digital samples are passed to the DDC (Digital Down Conversion) which converts digital IF samples into digital baseband samples (Referred as I/Q data). DDC consists of digital mixer, digital Local Oscillator (LO) and low pass FIR filter.

 

SDR Receiver architecture

 

The digital baseband samples are passed to the DSP chip where algorithms have been ported which does the functions such as demodulation, decoding and any other tasks if required. This digital implementation based architecture is referred as SDR or Software Defined Radio. Often FPGA is also used in place of DSP in this software-defined radio architecture for fast signal processing algorithms.

 

The software baseband processing chain on DSP/FPGA will help in correcting real-time baseband and RF-related impairments present in I/Q data with the use of advanced algorithms. Typically algorithms such as DC offset correction, I/Q gain and phase imbalance correction, time, frequency and channel impairment correction are implemented in the SDR receiver.

 

One of the key issues of the baseband processor is the amount of processing power required. The greater the level of processing, the higher the current consumption and in turn this required additional cooling, etc. This may have an impact on what can be achieved if power consumption and size are limitations.

 

Digital down converter

On the receiver side, digital IF techniques can be used to sample an IF signal and perform channelization and sample rate conversion in the digital domain. Using under-sampling techniques, high frequency IF signals, typically 100+ MHz, can be quantified. Proprietary Digital Down Converter (DDC) reference designs can be used as a design starting point or experimental platform. For SDR applications, since different standards have different chip/bit rates, non-integer sample rate conversion is required to convert the number of samples to an integer multiple of the fundamental chip/bit rate of any standard.

 

Digital IF Processing

To relax the direct analog modulation and demodulation specifications in radio frequency
(RF), baseband signals are converted to an intermediate frequency (IF) in the digital domain
followed by analog processing and vice versa.

 

Digital IF extends the scope of digital signal processing beyond the baseband domain out to the antenna, the RF domain, which increases system flexibility while reducing manufacturing costs. Moreover, digital frequency conversion provides greater flexibility and higher performance, in terms of attenuation and selectivity, than traditional analog techniques.

 

Data formatting – often required between the baseband processing elements and the upconverter – can be seamlessly added at the front end of the upconverter. This technique provides a fully customizable front end to the upconverter and allows for channelization of high-bandwidth input data, which is found in many 3G systems. Custom logic or an embedded processor can be used to control the interface between the upconverter and baseband processing element.

 

Digital IF modem designs fulfil an intermediate role between baseband and RF. It is an
essential part of the RF card solutions in wireless standards such as WiMAX, W-CDMA, and
LTE. With different wireless technologies evolving and shorter time to market, it is important
to build a system with flexibility for future upgrade and maintenance. An IF modem comprises of a digital upconverter (DUC) in the transmitter and a digital downconverter (DDC) in the receiver.

 

In a DUC, the complex baseband signals are interpolated to IF sampling rate and modulated up to selected IF carrier frequencies ranging from 0 Hz to (½sample rate -baseband bandwidth). Sometimes the IF carrier frequency is chosen as one-quarter of the sampling rate to further reduce hardware multiplier resource utilization.

 

For W-CDMA, you can choose to have one or more carriers transmitted using one antenna. The modulated up-converted signals are summed together before output to antenna. For WiMAX, there is no summation because there is only one carrier frequency.  In a DDC, the real IF signals are demodulated from selected carrier frequencies, and decimated to base band sampling rate.

 

Baseband processing

Wireless standards are continuously evolving to support higher data rates through the introduction of advanced baseband processing techniques such as adaptive modulation and coding, Space-Time Coding (STC), beam forming, and Multiple Input Multiple Output (MIMO) antenna techniques. Baseband signal processing devices require enormous processing bandwidth to support such computationally intensive algorithms. Proprietary FPGAs are tailored for applications such as channel coding for HSDPA and beam forming. The baseband components also must be flexible enough to enable SDR functionality that is required to support migration between enhanced versions of the same standard, as well as the capability to support a completely different standard.

 

Coprocessing features

SDR baseband processing often requires both processors and FPGAs, where the processor handles system control and configuration functions while the FPGA implements the computationally-intensive signal processing data path and control, minimizing the latency in the system. To go between standards, the processor can switch dynamically between major sections of software while the FPGA can be completely reconfigured, as necessary, to implement the data path for the particular standard.

 

Proprietary FPGA coprocessors interface with a wide range of DSP and general-purpose processors providing increased system performance and lower system costs. Complete proprietary system builder software can facilitate coprocessor integration, enabling designers to assemble parameterized blocks representing a plethora of functions ranging from muxes through fully parameterized FIR filters. Once a dataflow system has been captured, it can be exported for use as a coprocessor in any processor-based system assembled by the system builder software.

 

SDR Components and Their Respective Performance Parameters

ADCs and DACs

The ADC is a device that samples a continuous signal and generates codewords (digital bits) with a resolution that is equal to number of bits of the ADC. Sampling is done at the clock frequency. The DAC transforms codewords to analog signals, and is essentially opposite to what an ADC does. Some of the main performance parameters of commercial ADCs are resolution (bits), maximum sample rate, signal-to-noise ratio (SNR), spurious-free dynamic range (SFDR), serialization time, and current consumption. Ideally, an ADC’s SNR is six times its number of bits, that is, 8-bit, 10-bit and 12-bit ADCs would have SNRs of 48, 60 and 72 dB respectively. Similarly, the performance of a DAC can be quantified by its output voltage range, deserialization time, and current consumption. An ADC is a very critical SDR component, as it will have a significant effect on the dynamic range of the overall SDR system. The highest performance SDRs have 16-bit ADCs/DACs to ensure high SNR and SFDR.

 

Analog and Digital Filters

A filter is an important component in the radio front end of an SDR to separate the low, mid and high band chains of the circuit board. A filter is a device that removes noise and unwanted signal and/or frequency components. A filter that removes signals below a specific frequency is called a high pass filter because it “passes” higher frequencies, while a filter that removes signals above a specific frequency is known as a low pass filter. The specific frequency that lets all signals pass above or below is known as cutoff frequency of that high pass or low pass filter. A high pass and a low pass filter can be cascaded to form a band pass filter that will only pass a signal having frequency that lies in between the cutoff frequencies of both cascaded filters. Analog filters can be realized with analog electronic components such as resistors, capacitors/inductors, and op amps which become more complicated if you desire steeper roll-offs (or more accurate in their attenuation abilities).

 

Digital filters can be way more precise in their filtering functions, but the input signal must be digital. There are two main categories of digital filters, namely a digital finite impulse response (FIR) filter and a digital infinite impulse (IIR) filter. IIR filters take less digital memory and can be easily derived from analog filters, while, on the other hand, FIR filters take a lot of memory and are generally more complex than their analog or IIR counterparts, and require a very careful design. The main advantage of FIR over IIR filters is their inherent stability. Important filter parameters are cutoff frequency, stopband, side lobe level (the difference in dBs between pass band and stop band response), active/passive, linear or nonlinear, as well as others. In an SDR, digital filters are implemented in FPGAs and allow for more fine tuning of signals.

 

 

 

 

References and Resources also include:

https://www.ijert.org/research/contribution-to-the-development-of-a-reconfigurable-and-low-cost-multistandard-software-defined-radio-transceiver-for-the-new-radio-IJERTV10IS060381.pdf

http://signal-processing.mil-embedded.com/articles/fpga-software-defined-radio/

 

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