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Small Spacecraft Avionics

Small Spacecraft Avionics (SSA) are described as all electronic subsystems, components, instruments, and functional elements included in the spacecraft platform. These include primarily flight sub-elements Command and Data Handling (C&DH), Flight Software (FSW), and other critical flight subsystems, including Payload and Subsystems Avionics (PSA). All must be configurable into specific mission platforms, architectures, and protocols, and be governed by appropriate operations concepts, development environments, standards, and tools.

All spacecraft, require reliable, performant, and resource-efficient avionics to fulfill their mission successfully. Due to specific mission constraints and targets, high integration, as well as power and mass efficiency, are particularly important. One of the important goals is the standardization of interfaces, protocols, and algorithms in order to facilitate re-use and compatibility of individual building blocks.


• Increasing data rates: in space science and earth observation, more data generally means more science. Higher sampling rate, higher dynamic range, more spectral and spatial resolution, more channels and more auxiliary data enable scientific results of higher quality.
• More demand for on-board processing power: with growing data rates and data volumes, and physical and technological constraints for the available telemetry bandwidth, data reduction, compression and on-board pre-processing becomes more important.
• Low power consumption: many spacecraft operate in an environment where the availability of electrical power is very limited, and the cost of power in terms of spacecraft mass is very high. Therefore low power consumption is essential.
• Low mass: miniaturization of spacecraft systems is often an enabling factor for demanding space missions. This is also true for avionics elements, where miniaturization often goes hand in hand with a reduction of power consumption which allows achieving further mass savings.
• Low cost: an important factor for reducing avionics systems cost is the standardization of interfaces and building blocks which allows savings due to the re-use of avionics elements.
The reduction of mass and power consumption allows savings in other spacecraft system areas (power systems, structural mass, etc.) that may add up and allow significant overall cost savings.

The impact of significant miniaturization of avionics systems has been studied in the framework of a System on a Chip (SoC) study for a Jupiter Entry Probe (JEP). The effect of replacing traditional avionics elements by a SoC has been analyzed, and the impact on avionics mass, power, volume, operability, complexity, risk and cost of the probe has been studied. The study concluded that the estimated 5 kg saving in avionics mass would lead to a further 15 kg saving on other subsystems (power, structure, batteries, …) and lead to a smaller and lighter probe without a significant risk increase. Furthermore, a saving of 4% on the phase B/C/D cost was estimated, clearly showing the potential of avionics miniaturization for the design and development of challenging space missions.


Traditional spacecraft avionics have been designed around centralized architectures where each subsystem relies on a single processor whereby if one element fails, then the entire architecture commonly fails. This design often results in heavy weight, high power consumption, large volume, complex interfaces, and weak system reconfiguration capabilities. An open, distributed, and integrated avionics architecture with modular capability in software and hardware design is becoming more appealing for complex spacecraft development needs. In anticipation of extended durations in low-Earth orbit and deep space missions, vendors are now incorporating radiation hardened or radiation-tolerant architecture designs in their small spacecraft avionics packages to further increase their overall reliability.

As new generation avionics systems will integrate most of the electronic equipment on the spacecraft, an avionics system designed with networked real-time multitasking distributed system software, which can also implement dynamic reconfiguration of functions and task scheduling and improves the failure tolerance may minimize the need for expensive radiation-hardened electronic components. The improved avionics composition can include high-performance computing hardware to handle the large amount of anticipated data generated by more complex small spacecraft; embedded system software networked for real-time multitasking distributed system software; and software partition protection mechanisms. Some systems now implement a heterogeneous architecture in mixed criticality configurations, meaning they contain multiple processors with varying levels of performance and capabilities.

An example of new generation SSA/PSA distributed avionics application is the integration of Field Programmable Gate Arrays (FPGA)-based software defined radios (SDR) on small spacecraft. A software defined radio can transmit and receive in widely different radio protocols based on a modifiable, reconfigurable architecture, and is a flexible technology that can “enable the design of an adaptive communications system.” This can enable the small spacecraft to increase data throughput and provides the ability for software updates on-orbit, also known as re-programmability. Additional FPGA-based functional elements include imagers, AI/ML processors, and subsystem-integrated edge and cloud processors. The ability to reprogram sensors or instruments while on-orbit have benefited several CubeSat missions when instruments do not perform as anticipated, or they enter into an extended mission and subsystems or instruments need to be reprogrammed quickly.

The current generation of microprocessors can easily handle the processing requirements of most C&DH subsystems and will likely be sufficient for use in spacecraft bus designs for the foreseeable future. As small satellites move from the early CubeSat designs with short-term mission lifetimes to potentially longer missions, radiation tolerance also comes into play when selecting parts.  As spacecraft manufacturers begin to use more space qualified parts, they find that those devices can often lag their COTS counterparts by several generations in  performance but may be the only means to meet the radiation requirements placed on the system.

The form factors used in more traditional spacecraft designs frequently follow “plug into a backplane” VME standards. 3U boards offer a size (roughly 100 x 160 mm) and weight advantage over 6U boards (roughly 233 x 160 mm) if the design can be made to fit in the smaller form factor. The CompactPCI and PC/104 form factors continue generally to be the industry standard for CubeSat C&DH bus systems, with multiple vendors offering components that can be readily integrated into space rated systems. Overall form factors should fit within the standard CubeSat dimension of less than 10 x 10 cm.

A variety of vendors are producing highly integrated, modular, on-board computing systems for small spacecraft. These C&DH packages combine microcontrollers and/or FPGAs with various memory banks, and with a variety of standard interfaces for use with the other subsystems on board. The use of FPGAs and software-defined architectures also gives designers a level of flexibility to integrate uploadable software modifications to adapt to new requirements and interfaces.

The FPGA functions as the Main Control Unit, with interfaces to all functional subcomponents of a typical C&DH system. This then enables embedded, adaptive, and reprogrammable capabilities in modular, compact form factors, and provides inherent architectural capabilities for processor emulation, modular redundancies, and “software-defined-everything.”

Several radiation-hardened embedded processors have recently become available. These are being used as the core processors for a variety of purposes including C&DH. Some of these are the Vorago VA10820 (ARM M0) and the VA41620 and VA41630 (ARM M4); Cobham GR740 (quad core LEON4 SPARC V8) and the BAE 5545 quad core processor. These have all been radiation tested to at least 50 kRad total ionizing dose (TID).

The range of on-board memory for small spacecraft is wide, typically starting around 32 KB and increasing with available technology. For C&DH functions, on-board memory requires high reliability. A variety of different memory technologies have been developed for specific traits, including Static Random Access Memory (SRAM), Dynamic RAM (DRAM), flash memory (a type of electrically erasable, programmable, read-only memory), Magnetoresistive RAM (MRAM), Ferro-Electric RAM (FERAM), Chalcogenide RAM (CRAM) and Phase Change Memory (PCM). SRAM is typically used due to price and availability.

ESA reference avionics architecture

In the ESA reference avionics architecture, the interconnection of avionics elements and their components is achieved by a hierarchical concept that identifies different network and bus types providing specific services and data transfer rates. The currently existing top layer high speed network connectivity is provided by the SpaceWire (SpW)  network.

Spacewire (SpW)

The SpaceWire (SpW) interface is now a well-established standard interface for high datarate on-board networks. Its key features can be summarized as follows:
• Data rate up to 400 Mbps (200 Mbps typical)
• 9-pin Micro-miniature D-type connector, link cable length up to 10m (point-to-point)
• LVDS signalling, +/-350 mV typical, fault isolation properties
• 100 Ohm termination, power typically 50 mW per driver –receiver pair
• Established ECSS standard
• Simple, small IP (5-7 k logic gates)
• Supports simple P2P connections or complex networks via routers
• Supports time distribution with few μsec resolution
• supports Remote Memory Access Protocol (RMAP) data transfer

Complex SpW-based on-board networks need router chips for the interconnection of multiple nodes. Radhard chips are available from several manufacturers. ESA has supported the development of a router chip
which provides 8 full duplex SpW links supporting data rates of up to 200 Mbps.


MIL1553 bus

The MIL1553 bus is an established standard for the low data rate bus system. The MIL-STD-1553-B bus is used as a system platform bus on many space missions. It supports data rates up to 1 Mbit/sec and is extremely robust with respect to interference due to the high voltage levels and transformer coupling. This comes at the price of high power consumption and high harness mass. A low power and low mass alternative in particular for interplanetary missions is the CAN bus.

Controller Area Network (CAN)

Controller Area Network (CAN) bus is an efficient low data rate technology alternative for non-safety critical applications. The simple 2-wire interface allows low mass bus topologies, and the 1 Mbit/sec maximum data rate is sufficient for many low to medium bandwidth applications. Rad-hard bus interface components such as the ATMEL AT 7908E are available off-the-shelf, and many modern space electronics components provide built-in CAN bus interfaces.

At the lowest layer of the hierarchy, which is foreseen for hardware diagnostics and debugging, no specific interface or network standard has been developed; instead, the use of industry standard interfaces such as JTAG is encouraged.


For very high data rate connections and networks a fiberoptic link (SpaceFibre, SpFi) is being developed, which will provide even higher bandwidths beyond those provided by SpaceWire. The objectives and key performance characteristics are
• 1-10 Gbps data rate, 100m cable length, few g/m cable mass
• galvanic isolation (not provided by SpW)
• Copper version for small distances
• Transmission of a scalable number of SpW links over SpFi
• Compliance to SpW protocols and routing mechanisms


ESA is supporting a range of developments in the areas of avionics architectures, components, and onboard networks. Many of these developments are based on currently available design elements, architectural concepts, and standards. Attention is paid to the re-use of IP, standards compliance, backwards compatibility where it seems beneficial, and utilization of state-of-the-art manufacturing technologies


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