Intel has switched to 10nm manufacturing that can now pack more than 100 million (100.8 million, to be exact) transistors in each square millimeter of chip “for the first time in our industry’s history,” said Kaizad Mistry, a vice president and co-director of logic technology at the company. Delivering more transistors in the same area means the circuitry can be made smaller, saving on cost, or it means that more functionality can be added to a chip without having to make it bigger. 10nm is currently being commercialised by Intel, TSMC, GlobalFoundries, and Samsung.
The 10 nm generation specifications are 34 nm from one fin to the next in the company’s FinFET transistors and 36 nm from one wire to the next in the most dense interconnect layers (down from 42 nm and 52 nm, respectively, in the previous, 14-nm chip generation).
Moore’s Law which stated that the number of transistors on a chip will double approximately every two years has been the driver of semiconductor industry in boosting the complexity, computational performance and energy efficiency while reducing cost. It has led to substantial improvements in economic productivity and overall quality of life through proliferation of computers, communication, and other industrial and consumer electronics. Microelectronics and solid state components have also been the backbone of the military systems and were main contributors in advancement of radar, communication and electronic warfare systems.
On balance, Intel said, the company is still on a pace that roughly corresponds to a doubling of transistor density every couple of years. And by that metric, Bohr says, Intel has more than doubled its transistor density in recent years. From 22nm to 14nm, the transistor density jumped by a factor of 2.5x. And in the move from 14-nm to 10-nm chip manufacturing technology, the jump was 2.7x, from 37.5 million transistors per square millimeter to more than 100 million.
Moore’s Law is becoming more and more difficult. Transistors smaller than 7 nm will experience quantum tunnelling through their logic gates. Due to the costs involved in development, 5 nm is predicted to take longer to reach market than the 2 years estimated by Moore’s law.
Beyond 7 nm, major technological advances would have to be made; possible candidates include vortex laser,MOSFET-BJT dual-mode transistor, 3D packaging, microfluidic cooling, PCMOS, vacuum transistors,t-rays, extreme ultraviolet lithography, carbon nanotube transistors,silicon photonics, graphene, phosphorene, organic semiconductors, gallium arsenide, indium gallium arsenide, nano-patterning,and reconfigurable chaos-based microchips.
“You know one of the remarkable things about Moore’s Law is that Moore’s Law’s past seems preordained and ordinary, and Moore’s Law’s future is difficult and requires inventions,” Mistry told IEEE Spectrum.
Moore’s prediction is already slowing down and experts predict that will come to an end in the beginning of the 2020s. The minimum possible line width is expected to be 5 nm, which corresponds to about 20 silicon or copper atoms. The switching energy is approaching the thermal noise spectral density. In addition to noise, leakage currents and interconnects with high capacitances will form a problem. As dimensions approach nanometer ranges, CMOS transistors are difficult to operate because of rising power dissipation of chips and the fall in power gain of smaller transistors, soaring fabrication plant costs and finally, quantum effects in silicon will bring about an end to the ongoing miniaturization of CMOS transistors.
Handel Jones, the CEO of International Business Strategies, reckons that a fab for state-of-the-art microprocessors now costs around $7 billion. He thinks that by the time the industry produces 5nm chips (which at past rates of progress might be in the early 2020s), this could rise to over $16 billion, or nearly a third of Intel’s current annual revenue.
Intel calls the suite of strategies it uses to accomplish this more-than-doubling “hyperscaling.” It includes design improvements, but a big piece is the company’s approach to laying down the patterns that ultimately become the chip’s transistors and wiring.
With 10-nm chips, Intel as adopted self-aligned quadruple patterning (SAQP), a similar approach that requires four passes through a lithography machine. Mistry says SAQP has one more generation in it, which would take Intel down to the feature sizes needed to produce the next generation: 7 nm.
Somewhere in there, we may just see extreme ultraviolet (EUV) lithography enter the picture. EUV uses 13.5-nm radiation (pretty much X-rays) instead of 193-nm ultraviolet light for feature patterning.
In 2015, Intel described a lateral nanowire (or gate-all-around) FET concept for the 5-nm node. In 2016, researchers at Berkeley Lab created a transistor with a working 1-nanometer gate. The field-effect transistor utilized MoS2 as the channel material, while a carbon nanotube was used to invert the channel. The effective channel length is approximately 1 nm. However, the drain to source pitch was much bigger, with micrometer size.
More Moore technologies
One idea is to try to keep Moore’s law going by moving it into the third dimension. Modern chips are essentially flat, but researchers are toying with chips that stack their components on top of each other. Even if the footprint of such chips stops shrinking, building up would allow their designers to keep cramming in more components, just as tower blocks can house more people in a given area than low-rise houses. Intel has incorporated the materials into new 3-D devices, called FinFETs, which have channels that pop out of the plane of the wafer.
However 3D chip would require new cooling technique as the surface area available to remove heat would grow much more slowly than the volume that generates it. One of the technology proposed is liquid cooling. Microscopic channels would be drilled into each chip, allowing cooling liquid to flow through.
There are also problems with getting enough electricity and data into such a chip , he firm believes that the coolant can double as a power source. The idea is to use it as the electrolyte in a flow battery, in which electrolyte flows past fixed electrodes.
The vision of “More Moore” Technologies is to continue to follow the exponential reduction in size of electronic devices by migrating from charge to non-charge based devices i.e. based on spin, molecular state, photons, phonons, nanostructures, mechanical state, resistance, quantum state (including phase) and magnetic flux.
According to Semi engineering, the industry is evaluating a wide range of technologies for the sub-10nm node including gate-all-around FETs (also called nanowires), quantum well FETs, and silicon-on-insulator FinFETs.
IBM Announces Breakthrough in Chip Technology
IBM, working with GlobalFoundries, Samsung, SUNY, and various equipment suppliers, has produced the world’s first 7nm chip with functional transistors. The transistors are of the FinFET variety, with one significant difference over commercialised FinFETs: the channel of the transistor is a silicon-germanium (SiGe) alloy, rather than just silicon. SiGe has higher electron mobility than pure silicon, which makes it better suited for smaller transistors. To reach such tiny geometries, self-aligned quadruple patterning (SAQR) and EUV lithography is used.
IBM says it has overcome a technological hurdle by producing a prototype chip with transistors that are just 7 nanometers wide, or about 1/10,000th the width of a human hair. The breakthrough occurred at SUNY Polytechnic Institute’s Colleges of Nanoscale Science and Engineering. It could result in the ability to place 20 billion transistors on a chip the size of a fingernail.
Ars Technica reports: “While it should be stressed that commercial 7nm chips remain at least two years away, this test chip from IBM and its partners is extremely significant for three reasons: it’s a working sub-10nm chip (this is pretty significant in itself); it’s the first commercially viable sub-10nm FinFET logic chip that uses silicon-germanium as the channel material; and it appears to be the first commercially viable design produced with extreme ultraviolet (EUV) lithography.”
Based on the current calculations, today’s finFET could run out of gas at 5nm, prompting the need for a new technology. Two types of FET’s, the Si-nanowire FET and the alternative channel (such as GaAs and Ge) FET, have shown promise to replace current planer bulk CMOS. The Si-nanowire FET has higher on-current conduction due to their quantum nature and would have edge for adoption and more promising due to its compatibility with current Si CMOS process technologies.
Tunneling FET (TFET) employs quantum mechanical band-to-band tunneling mechanism having low power and FET structure that is compatible with CMOS technology. Resonant Tunneling Diodes (RTD) can provide high speed bi-stable logic operation and tunneling based SRAMs. Single Electron Transistor (SET) provides high speed, high device density, and high power efficiency and is also compatible with CMOS.
Carbon nanotube transistors
The most matured technology to take over silicon is the single-walled carbon nanotube, a rolled-up sheet of linked carbon atoms. Unlike its two-dimensional cousin, graphene, the carbon nanotube can be a natural semiconductor, which means it can be turned on and off to make a binary switch and it’s long been eyed as a potential material for speedy and energy-efficient switches. A carbon-nanotube transistor looks much the same as a silicon transistor. The main difference is that the channel is made of carbon nanotubes instead of silicon.
IBM scientists demonstrated a new way to shrink transistor contacts without reducing performance of carbon nanotube devices, opening a pathway to dramatically faster, smaller and more powerful computer chips beyond the capabilities of traditional semiconductors. These results could overcome contact resistance challenges all the way to the 1.8 nanometer node – four technology generations away.
The success of the new method means that the ability to deliver current to carbon nanotube transistors is now independent of the length of the metal contacts, says Wilfried Haensch, who leads IBM Research’s nanotube project. It’s now clear they can make the transistors as small as necessary, he says, and this is a big step toward the company’s goal of having carbon nanotube technology ready by 2020
Spintronics is “A branch of physics concerned with the storage and transfer of information by means of electron spins in addition to electron charge as in conventional electronics.” Spin-based electronics focuses on devices whose functionality is based primarily on the spin degree of freedom of the carriers. This is in contrast to conventional electronics, which exploits only the charge of the carriers.
Using either the spin in tandem with the charge or alone, spintronics has some advantages over conventional semiconductor electronics, including higher integration density, non-volatility, decreased power dissipation and faster processing speeds.
Nanoribbons have potential application in fabrication of spintronics. They shall be enabled by bottom up electronics, shall utilize two-dimensional (2D) Materials such as Graphene, MoS2, one-dimensional (1D) Materials such as Carbon Nanotubes and nanowires of Si, Ge, InAs, and Metal Oxides etc. Even zero-dimensional (0D) materials such as Quantum Dots and Molecular Electronics are being researches to take ultimate benefit from advantages of quantum phenomenon.
New spintronics breakthrough paves the way to faster computing
Researchers have achieved all-electric control of the spin of electrons in a major breakthrough that brings much faster and more efficient spintronics-based computation closer than ever before. Because a spinning electrically charged particle like an electron has well-known magnetic properties, the most natural way to control electronic spin is to use ferromagnetic materials embedded in spintronic devices. This, however, makes the devices very bulky, which is clearly the opposite of the direction towards which technological progress is pushing.
Led by Dr. Debray, the UC team managed to control the spin of electrons traveling on a wire with an all electrical device for the very first time, reaching a milestone in this new and very promising field that is important mainly because it allows for much smaller spintronic devices to be built.
The team used an indium arsenide “quantum point contact,” a wire only a few hundred nanometers in length whose conductivity can be modified by regulating the voltages at its two ends. The asymmetry that comes from setting two different voltages at the two ends (gates) allows the electrons to become polarized as they enter the wire.
Deep Neural networks or large virtual networks of simple information-processing units, which are loosely modeled on the anatomy of the human brain have been responsible for many exciting advances in artificial intelligence in recent years.”Deep learning is useful for many applications, such as object recognition, speech, face detection,” says Vivienne Sze, the Emanuel E. Landsman Career Development Assistant Professor in MIT’s Department of Electrical Engineering and Computer Science whose group developed the new type of deep-learning chip that dramatically speeds up the ability of neural networks to process and identify data.
At the International Solid State Circuits Conference in San Francisco, MIT researchers presented a new chip designed specifically to implement neural networks. It is 10 times as efficient as a mobile GPU, so it could enable mobile devices to run powerful artificial-intelligence algorithms locally, rather than uploading data to the Internet for processing.
UK-based startup Optalysys promises optical processors for supercomputers
Optalysys has completed 320 gigaFLOP optical computer prototype, targets 9 petaFLOP product in 2017 and 17 exaFLOPS machine by 2020 .
“Optalysys’ technology applies the principles of diffractive and Fourier optics to calculate the same processor intensive mathematical functions used in CFD (Computational Fluid Dynamics) and pattern recognition,” Dr. Nick New, CEO and founder of the company explained. “Using low power lasers and high resolution liquid crystal micro-displays, calculations are performed in parallel at the speed of light,” New further described.
The Optalysys Optical Solver Supercomputer reduces energy footprint so it can be considered as eco-efficient as well. No need for special power as it only needs a standard mains power supply. As for the running cost, the super processor only costs £2,100 every year. This is way cheaper than the fast supercomputer available in China, the Tianhe-2, developed by the National University of Defense Technology. The computer alone costs $320 million but with a $21m annual running cost.
Quantum computing and quantum information processing are next revolutionary technology expected to have immense impact. Quantum computers will be able to perform tasks too hard for even the most powerful conventional supercomputer and have a host of specific applications, from code-breaking and cyber security to medical diagnostics, big data analysis and logistics. Quantum computers could accelerate the discovery of new materials, chemicals and drugs. They could dramatically reduce the current high costs and long lead times involved in developing new drugs.
Recently biocomputers are becoming feasible due to advancements in nanobiotechnology. Nanobiotechnology can be defined as any type of technology that uses both nano-scale materials (i.e. materials having characteristic dimensions of 1-100 nanometers) and biologically based materials. Biocomputers use systems of biologically derived molecules—such as DNA and proteins—to perform computational calculations involving storing, retrieving, and processing data. The economical benefit of biocomputers lies in potential of all biologically derived systems to self-replicate and self-assemble into functional components given appropriate conditions.
DARPA’s Semiconductor Technology Advanced Research Network (STARnet)
Semiconductor Research Corporation (SRC) and the Defense Advanced Research Projects Agency (DARPA) has launched a $194 million initiative, the Semiconductor Technology Advanced Research Network (STARnet) to help maintain U.S. leadership in semiconductor technology that is vital to U.S. prosperity, security and intelligence. Two of the six academic teams are following:
Function Accelerated Nanomaterial Engineering (FAME): The FAME Center hosted at the University of California-Los Angeles, focuses on nonconventional materials and devices incorporating nanostructures with quantum-level properties to enable analog, logic and memory devices for beyond-binary computation.
Center for Spintronic Materials, Interfaces, and Novel Architectures (C_SPIN): C_SPIN hosted at the University of Minnesota focuses on magnetic materials, spin transport, novel spin-transport materials, spintronic devices, circuits and novel architectures and create the fundamental building blocks that allow revolutionary spin-based multi-functional, scalable memory devices and computational architectures to be realized.
“Without the nanoelectronics sector there would be no viable defence sector, and without defence, investment in nanoelectronics would not be feasible”, said Michael Sieber, EDA assisting one roundtable.
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