Today’s leading edge electronic designs are complex, expensive, and often involve teams spread across the globe; factors that have driven drastic growth in non-recurring engineering (NRE) costs. Additionally, the monolithic nature of these designs means that any change to a portion of the chip requires a re-spin of the entire chip. The high cost notwithstanding, these application specific integrated circuits (ASICs) are unrivaled in their performance. Many large commercial designers can spread these costs over the large volumes of consumer products, but for low-volume customers like the DoD, start-up companies, and academia, these mounting costs have restricted access to the latest device technologies (or “nodes”).
DARPA launched “CHIPS,” or Common Heterogeneous Integration and Intellectual Property (IP) Reuse Strategies Program with aim to devise a physical library of component chips, or chiplets, that can be assembled in a modular fashion. The library of custom and commercial “chiplets” shall individually embody a particular function, such as data storage, computation, signal processing, and managing the form and flow of data. By assembling and integrating dozens of chiplets, mosaic style, on a so-called interposer, which is like a printed circuit board writ small, all of those microsystems’ functions could be performed in a much closer huddle and can perform more efficiently than if they were distributed in the usual way among a suite of chips attached to a conventional PCB.
“We are trying to push the massive amount of integration you typically get on a printed circuit board(PCB) down into an even more compact format,” Dr. Daniel Green, manager of the new program said.
DARPA held the kickoff meeting for its new CHIPS program where a dozen prime contractors have been named, among them Intel, Micron, and Cadence Design Systems. The other designated contractors include Lockheed Martin, Northrop Grumman, and Boeing, Synopsys, Intrinsix Corp., and Jariet Technologies, University of Michigan, Georgia Institute of Technology, and North Carolina State University. Central to the design and intention of the program, says DARPA, is the creation of a new community of researchers and technologists that mix-and-match mindsets, skillsets, technological strengths, and business interests. The prime contractors are expected to help build this community by working with others.
Chips is part of a larger DARPA effort, the Electronics Resurgence Initiative, which aims to build an electronics community that mixes the best of the commercial and defense capabilities for national defense. The ERI will involve an expenditure of at least $200 million annually over the next four years.
The foundation for the Initiative has been building for a number of years in the form of existing MTO programs such as DAHI, CHIPS and CRAFT, which address ERI’s three research pillars: materials and integration, circuit design, and systems architecture. Another major ERI component is the extensive university-based program—the Joint University Microelectronics Program (JUMP)—that MTO and corporate partners have organized to build up a fundamental research base in fields underlying microelectronic technologies.
Modular and Open Architecture for Third offset Strategy
DARPA’s Common Heterogeneous Integration and Intellectual Property (IP) Reuse Strategies Program is also in line with US’s third offset strategy, which according to Hagel is “This new initiative is an ambitious department-wide effort to identify and invest in innovative ways to sustain and advance America’s military dominance for the 21st century.” “Fundamentally, what’s behind the push of the Third Offset Strategy is this idea that the department needs to reinvigorate our ability to develop these advanced technologies,” Prabhakar said. “If we do that at the same old pace in the same old way, there’s a strong recognition that we’re just not going to get there.”
Instead of such custom-tailored, tightly integrated systems, you want a modular and open architecture where you can easily replace a component — hardware or software — without disrupting the rest of the system. Instead of a relatively small number of pricey manned platforms, you want a “heterogeneous” mix of manned and unmanned vehicles of all kinds, from 130-foot robotic ships to disposable handheld drones. Instead of architectures designed for a specific kind and size of force, you want systems that can scale up and down as the force changes.
DARPA’s “CHIPS,” or Common Heterogeneous Integration and Intellectual Property (IP) Reuse Strategies Program
A primary driver of CHIPS is to develop a novel, industry-friendly architectural strategy for designing and building new generations of microsystems in which the time and energy it takes to move signals—that is, data—between chips is reduced by factors of tens or even hundreds. “This is increasingly important for the data-intensive processing that we have to do as the data sets we are dealing with get bigger and bigger,” Green said. The new architectural strategy at the program’s heart could open new routes to computational efficiencies required for such feats as identifying objects and actions in real-time video feeds, real-time language translation, and coordinating motion on-the-fly among swarms of fast-moving unmanned aerial vehicles (UAVs).
One technique for addressing rising cost and complexity has been the use of a modular design flow that subdivides a system into functional circuit blocks, called IP blocks. IP block refers to intellectual property captured in a pre-designed functional circuit block. Examples of IP blocks include, but are not limited to, timing circuits, filters, waveform generators, embedded processors, data converters, amplifiers, fast Fourier transforms (FFTs), serializer-deserializers (SERDES), and memory.
Another problem DARPA’s trying to solve is the cost and complexity of intellectual property (IP). Using a standard circuit board often requires the manufacturer to buy multiple patent licenses for unneeded functions. The US Department of Defense thinks that if chiplets are separated by function, it would reduce costs by limiting the required IP. “This should be a win for both the commercial and defense sectors,” DARPA’s Dr. Daniel Green asserts.
DARPA has posted a Request for Information (RFI), designated on fbo.gov as DARPA-SN-16-50, to harvest ideas at the front-end of the program from expert and industry players so that the CHIPS team can hone the details of the program in ways that would facilitate graceful incorporation of these new approaches within existing commercial semiconductor foundries and electronics fabrication facilities.
DARPA seeks innovative insights on how standard interfaces and IP reuse can be to create custom circuits in a fraction of today’s time and cost, with conventional methods for both digital and analog systems.
“Key to the success of CHIPS will be standards and interfaces, and this means we will be working with a community, not all by ourselves,” said Green. The CHIPS team expects to use input from the RFI and a workshop anticipated to occur later this summer to prepare a Broad Agency Announcement (BAA). The BAA, which will also be posted on fbo.gov, will specify the program’s technical goals and how potential performers can submit proposals.
Diverse Accessible Heterogeneous Integration (DAHI)
Complex Defense systems, such as RADAR, communications, imaging and sensing systems rely on a wide variety of microsystems devices and materials. These diverse devices and materials typically require different substrates and different processing technologies, preventing the integration of these devices into single fabrication process flows. Thus, integration of these device technologies has historically occurred only at the chip-to-chip level, which introduces significant bandwidth and latency-related performance limitations on these systems, as well as increased size, weight, power, and packaging/assembly costs as compared to microsystems fully integrated on a single chip.
The development of compound semiconductor (CS) electronics has been motivated by their many superior materials properties relative to silicon. For example, high electron mobility and peak velocity of InP-based material systems have resulted in transistors with fmax above 1THz as well as ultra-high-speed mixed-signal circuits. The wide energy bandgap of GaN has enabled large voltage swings as well as high breakdown voltage RF power devices. Excellent thermal conductivity of SiC also makes tens of kilowatt-level power switches possible. Meanwhile, in the photonics domain, III-V materials based on InP and GaAs have been a key enabler due to the excellent photonic properties associated with the direct band gap of these materials. The indirect band gap of silicon makes optical gain in this material very inefficient, greatly limiting its utility in both discrete and integrated photonic systems. On the other hand, silicon CMOS-based technologies have achieved tremendous levels of complexity and integration, while also demonstrating high levels of yield and manufacturability.
The DAHI program is developing transistor-scale heterogeneous integration processes to intimately combine advanced compound semiconductor (CS) devices, as well as other emerging materials and devices, with high-density silicon complementary metal-oxide-semiconductor (CMOS) technology.
This technology is currently enabling RF/mixed signal circuits with revolutionary performance. For example, InP HBT + CMOS technology is being utilized in advanced DACs and ADCs with CMOS-enabled calibration and self-healing techniques for correcting static and dynamic errors in situ. Such CMOS-enabled self-healing techniques are expected to more generally enable improved CS-based circuit performance and yield in the presence of process and environmental variability, as well as aging. DAHI is also expected to enable the integration of high power CS devices with silicon-based linearization techniques to realize highly power efficient transmitters. By enabling this heterogeneous integration capability, DAHI seeks to establish a new paradigm for microsystems designers to utilize a diverse array of materials and device technologies on a common silicon-based platform.
The ultimate goal of DAHI is to establish a manufacturable, accessible foundry technology for the monolithic heterogeneous co-integration of diverse devices and complex silicon-enabled architectures on a common substrate platform. Such integration would increase the capabilities of high-performance microsystems for the U.S. Military. The DAHI program will address the following key technical challenges (1) heterogeneous integration process development, (2) high-yield manufacturing and foundry establishment, and (3) circuit design and architecture innovation.
Microsystem devices and materials that may be integrated include:
- Silicon complementary metal-oxide-semiconductor (Si CMOS) for highly integrated analog and digital circuits
- Gallium Nitride (GaN) for high-power/high-voltage swing and low-noise amplifiers
- Gallium Arsenide (GaAs) and Indium Phosphide (InP) heterojunction bipolar transistors (HBT) and high-electron mobility transistors (HEMT) for high speed/high-dynamic-range/low-noise circuits
- Antimonide-based compound semiconductors for high-speed, low-power electronics
- Compound semiconductor optoelectronic devices for direct-bandgap photonic sources and detectors, as well as or silicon-based structures for modulators, waveguides, etc.
- Microelectromechanical (MEMS) components for sensors, actuators and RF resonators
- Thermal management structures
DARPA’s efforts in heterogeneous integration began with the Compound Semiconductor Materials on Silicon (COSMOS) program. COSMOS is now a DAHI program thrust, along with Electronic-Photonic Heterogeneous Integration (E-PHI) and DAHI Foundry Technology thrusts.
DARPA’s CRAFT Program Aims for Affordable Designer Circuits that Do More with Less Power
Demand for specialized integrated circuits for military electronics continues to surge exponentially with no end in sight. Systems that synchronize the activity of unmanned aerial vehicles; real-time conversion of raw radar data into tactically useful 3-D imagery; and instant access to high-resolution sensor feeds on the battlefield are only three examples of this reality. Despite the importance of these capabilities to national security, however, current circuit-design methods often result in devices that require more power than can be practically supplied on small flying platforms or on warfighters already burdened by too much battery weight.
It’s not that engineers are incapable of designing custom integrated circuits that can perform a specific task with optimum power efficiency. It is, rather, that they are today stymied by the prospect of spending up to $100 million and working for more than two years to complete such a design. As a result, Defense Department engineers often turn to more generic, inexpensive, and readily available general-purpose circuits, and then rely on software to make those circuits run the required specialized operations. Using general-purpose circuits can speed up design and implementation, but also burdens electronic systems with unnecessary power-gobbling circuitry.
“This dilemma has reduced the use of custom-integrated circuits and, consequently, the performance of DoD systems,” according to BAA of the three-phase program, Circuit Realization At Faster Timescales (CRAFT), that was slated to last just over three years with total funding of about $30 million. Overseen by Linton Salmon, a program manager in DARPA’s Microsystems Technology Office (MTO), the CRAFT program seeks to develop new fast-track circuit-design methods, multiple sources for integrated circuit fabrication, and a technology repository that will facilitate reuse of proven solutions.
Many systems could benefit from advances of the sort that CRAFT seeks to catalyze. Consider, for example, the data- and computation-intensive “Gotcha” radar system that the Air Force Research Laboratory is developing to identify moving objects over city-scale areas and render detailed 3-D imagery. “Gotcha currently requires a land-based supercomputer to make sense of the radar data and convert it into tactically useful imagery. However, relaying the data to a remote supercomputer across a contested data link can cause crippling delays,” Salmon explained. “The CRAFT program could help put more of the necessary computational power on the UAV itself or on the backs of warfighters, enabling quicker delivery of the imagery to those who need it most.”
At the core of the CRAFT vision is an unprecedented ability to fabricate customized, technology-specific circuits using the 16 nanometer/14 nm commercial fabrication infrastructure that today produces generic commodity circuits. “A custom integrated circuit designed only to process images from an airborne radar or to analyze sensor data for warfighters on the ground doesn’t need to run a spread sheet or a word processor,” Salmon said. “Why carry around a heavy bulging Swiss Army knife when all you need is a single Phillips-head screwdriver?”
Being able to jettison the massive amounts of circuitry dedicated to everyday functions would allow the resulting spare capability to be devoted to crucial functions, Salmon continued. “In the end,” he said, “you would have a top-of-the-line, custom-integrated circuit that does only the job you need and does so much more effectively.”
To achieve its goals, CRAFT seeks to shorten the design cycle for custom integrated circuits by a factor of 10 (on the order of months rather than years); devise design frameworks that can be readily recast when next-generation fabrication plants come on line; and create a repository so that methods, documentation and intellectual property need not be reinvented with each design and fabrication cycle.
“If CRAFT is successful, design of custom integrated circuits will be far more readily available to those building DoD systems,” Salmon said. “As a result, engineers will be able to make decisions based on the best technical solutions for the systems they are building, instead of worrying about circuit design delays or costs.”
Officials of the U.S. Defense Advanced Research Projects Agency (DARPA) in Arlington, Va., announced AN $8.2 million contract modification to the USC Information Sciences Institute (ISI) in Los Angeles in Aug 2017 for phase-two options in the Circuit Realization at Faster Timescales (CRAFT) – FinFET Foundry/Design Aggregation Services military chips program.
USC ISI won an $11.8 million contract in December 2015 for the first phase of the CRAFT FinFET program. USC ISI then won $3 million in CRAFT FinFET contract options in March 2016 — $1.2 million for phase 1, $890,524 for phase 2 option 1, and $840,335 for phase 3 option 2.
The CRAFT FinFET program seeks to develop a custom IC design flow to reduce the effort necessary to design high-performance custom ICs; help port IC designs to secondary IC foundries and more advanced technologies; and reuse of IC intellectual property.
In the program’s first phase USC experts will have demonstrated a 10X reduction in design efforts using a standard flow for a system-on-chip (SoC) with logic block size of more than 200,000 gates; several mixed signal blocks, SRAM memory blocks, and third-party intellectual property (IP) blocks.
In the second phase, USC experts will demonstrate a 7X reduction in design efforts to create a DARPA-selected SoC design, document the design flow; test fabricated chip functionality across standard temperature ranges; characterize an initial suite of macros and generators; document a reference CAD flow; and design a suite of macro and generators.